one-byte quick reference

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

two-byte (0F..) quick reference

00 01 02 03 05 06 07 08 09 0B 0D 1F 20 21 22 23 24 26 30 31 32 33 34 35 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 60 61 62 63 64 65 66 67 68 69 6A 6B 6E 6F 71 72 73 74 75 76 77 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C7 C8 C9 CA CB CC CD CE CF D1 D2 D3 D5 D8 D9 DB DC DD DF E1 E2 E5 E8 E9 EB EC ED EF F1 F2 F3 F5 F8 F9 FA FC FD FE
pf0Fposofldsoprocstmrlxmnemonicop1op2op3op4iextgrp1grp2grp3tested fmodif fdef fundef ff valuesdescription, notes                                                  
00dwrLADDEbGbgen arithbinaryo..szapco..szapcAdd
01dWrLADDEvqpGvqpgen arithbinaryo..szapco..szapcAdd
02DwrADDGbEbgen arithbinaryo..szapco..szapcAdd
03DWrADDGvqpEvqpgen arithbinaryo..szapco..szapcAdd
04wADDALIbgen arithbinaryo..szapco..szapcAdd
05WADDrAXIvdsgen arithbinaryo..szapco..szapcAdd
06srPUSHESgen stack segregPush Word, Doubleword or Quadword Onto the Stack
06P4+EinvalidInvalid Instruction in 64-Bit Mode
07srPOPESgen stack segregPop a Value from the Stack
07P4+EinvalidInvalid Instruction in 64-Bit Mode
08dwrLOREbGbgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
09dWrLOREvqpGvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
0ADwrORGbEbgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
0BDWrORGvqpEvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
0CwORALIbgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
0DWORrAXIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
0EsRPUSHCSgen stack segregPush Word, Doubleword or Quadword Onto the Stack
0EP4+EinvalidInvalid Instruction in 64-Bit Mode
0FsR00D1POPCSgen stack segregPop a Value from the Stack
0F01invalid
0F02+two-byte
10dwrLADCEbGbgen arithbinary.......co..szapco..szapcAdd with Carry
11dWrLADCEvqpGvqpgen arithbinary.......co..szapco..szapcAdd with Carry
12DwrADCGbEbgen arithbinary.......co..szapco..szapcAdd with Carry
13DWrADCGvqpEvqpgen arithbinary.......co..szapco..szapcAdd with Carry
14wADCALIbgen arithbinary.......co..szapco..szapcAdd with Carry
15WADCrAXIvdsgen arithbinary.......co..szapco..szapcAdd with Carry
16SrPUSHSSgen stack segregPush Word, Doubleword or Quadword Onto the Stack
16P4+EinvalidInvalid Instruction in 64-Bit Mode
17SrPOPSSgen stack segregPop a Value from the Stack
17P4+EinvalidInvalid Instruction in 64-Bit Mode
18dwrLSBBEbGbgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
19dWrLSBBEvqpGvqpgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
1ADwrSBBGbEbgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
1BDWrSBBGvqpEvqpgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
1CwSBBALIbgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
1DWSBBrAXIvdsgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
1ESRPUSHDSgen stack segregPush Word, Doubleword or Quadword Onto the Stack
1EP4+EinvalidInvalid Instruction in 64-Bit Mode
1FSRPOPDSgen stack segregPop a Value from the Stack
1FP4+EinvalidInvalid Instruction in 64-Bit Mode
20dwrLANDEbGbgen logicalo..szapco..sz.pc.....a..o......cLogical AND
21dWrLANDEvqpGvqpgen logicalo..szapco..sz.pc.....a..o......cLogical AND
22DwrANDGbEbgen logicalo..szapco..sz.pc.....a..o......cLogical AND
23DWrANDGvqpEvqpgen logicalo..szapco..sz.pc.....a..o......cLogical AND
24wANDALIbgen logicalo..szapco..sz.pc.....a..o......cLogical AND
25WANDrAXIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical AND
26ESESprefix segregES segment override prefix
26P4+undefinedprefix branchcond(use with any branch instruction is reserved)
26P4+Enullprefix segregNull Prefix in 64-bit Mode
27DAAALgen arithdecimal.....a.co..szapc...szapco.......Decimal Adjust AL after Addition
27P4+EinvalidInvalid Instruction in 64-Bit Mode
28dwrLSUBEbGbgen arithbinaryo..szapco..szapcSubtract
29dWrLSUBEvqpGvqpgen arithbinaryo..szapco..szapcSubtract
2ADwrSUBGbEbgen arithbinaryo..szapco..szapcSubtract
2BDWrSUBGvqpEvqpgen arithbinaryo..szapco..szapcSubtract
2CwSUBALIbgen arithbinaryo..szapco..szapcSubtract
2DWSUBrAXIvdsgen arithbinaryo..szapco..szapcSubtract
2ECSCSprefix segregCS segment override prefix
2EP4+NTAKENprefix branchcondBranch not taken prefix (used only with Jcc instructions)
2EP4+Eundefinedprefix branchcond(branch hint prefixes have no effect in 64-bit mode)
2EP4+Enullprefix segregNull Prefix in 64-bit Mode
2FDASALgen arithdecimal.....a.co..szapc...szapco.......Decimal Adjust AL after Subtraction
2FP4+EinvalidInvalid Instruction in 64-Bit Mode
30dwrLXOREbGbgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
31dWrLXOREvqpGvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
32DwrXORGbEbgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
33DWrXORGvqpEvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
34wXORALIbgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
35WXORrAXIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
36SSSSprefix segregSS segment override prefix
36P4+undefinedprefix branchcond(use with any branch instruction is reserved)
36P4+Enullprefix segregNull Prefix in 64-bit Mode
37AAAALAHgen arithdecimal.....a..o..szapc.....a.co..sz.p.ASCII Adjust After Addition
37P4+EinvalidInvalid Instruction in 64-Bit Mode
38dwrCMPEbGbgen arithbinaryo..szapco..szapcCompare Two Operands
39dWrCMPEvqpGvqpgen arithbinaryo..szapco..szapcCompare Two Operands
3ADwrCMPGbEbgen arithbinaryo..szapco..szapcCompare Two Operands
3BDWrCMPGvqpEvqpgen arithbinaryo..szapco..szapcCompare Two Operands
3CwCMPALIbgen arithbinaryo..szapco..szapcCompare Two Operands
3DWCMPrAXIvdsgen arithbinaryo..szapco..szapcCompare Two Operands
3EDSDSprefix segregDS segment override prefix
3EP4+TAKENprefix branchcondBranch not taken prefix (used only with Jcc instructions)
3EP4+Eundefinedprefix branchcond(branch hint prefixes have no effect in 64-bit mode)
3EP4+Enullprefix segregNull Prefix in 64-bit Mode
3FAASALAHgen arithdecimal.....a..o..szapc.....a.co..sz.p.ASCII Adjust AL After Subtraction
3FP4+EinvalidInvalid Instruction in 64-Bit Mode
40+rINCZvgen arithbinaryo..szap.o..szap.Increment by 1
40P4+EREXprefix
41P4+EREX.BprefixExtension of the r/m field, base field, or opcode reg field
42P4+EREX.XprefixExtension of the SIB index field
43P4+EREX.XBprefix
44P4+EREX.RprefixExtension of the ModR/M reg field
45P4+EREX.RBprefix
46P4+EREX.RXprefix
47P4+EREX.RXBprefix
48+rDECZvgen arithbinaryo..szap.o..szap.Decrement by 1
48P4+EREX.Wprefix64 Bit Operand Size
49P4+EREX.WBprefix
4AP4+EREX.WXprefix
4BP4+EREX.WXBprefix
4CP4+EREX.WRprefix
4DP4+EREX.WRBprefix
4EP4+EREX.WRXprefix
4FP4+EREX.WRXBprefix
50+rPUSHZvgen stackPush Word, Doubleword or Quadword Onto the Stack
50+rP4+EPUSHZvqgen stackPush Word, Doubleword or Quadword Onto the Stack
58+rPOPZvgen stackPop a Value from the Stack
58+rP4+EPOPZvqgen stackPop a Value from the Stack
6001+PUSHA ... gen stackPush All General-Purpose Registers
6003+PUSHA ... gen stackPush All General-Purpose Registers
PUSHAD ...
60P4+EinvalidInvalid Instruction in 64-Bit Mode
6101+POPA ... gen stackPop All General-Purpose Registers
6103+POPA ... gen stackPop All General-Purpose Registers
POPAD ...
61P4+EinvalidInvalid Instruction in 64-Bit Mode
62Dr01+fBOUNDGvMaFvgen break stack..i.......i.......i.....Check Array Index Against Bounds
62P4+EinvalidInvalid Instruction in 64-Bit Mode
63r02+ARPLEwGwsystem....z.......z...Adjust RPL Field of Segment Selector
63DrP4+EMOVSXDGdqpEdsgen converMove with Sign-Extension
6403+FSFSprefix segregFS segment override prefix
64P4+undefinedprefix branchcond(used only with Jcc instructions)
64P4+U2ALTERprefix branchcondAlternating branch prefix (used only with Jcc instructions)
64P4+Eundefinedprefix branchcond(branch hint prefixes have no effect in 64-bit mode)
6503+GSGSprefix segregGS segment override prefix
65P4+undefinedprefix branchcond(used only with Jcc instructions)
66no mnemonicprefixOperand-size override prefix
66P4+Mno mnemonicsse2prefixPrecision-size override prefix
67no mnemonicprefixAddress-size override prefix
6801+PUSHIvsgen stackPush Word, Doubleword or Quadword Onto the Stack
6901+IMULGvqpEvqpIvdsgen arithbinaryo..szapco......c...szap.Signed Multiply
6AS01+PUSHIbssgen stackPush Word, Doubleword or Quadword Onto the Stack
6BS01+IMULGvqpEvqpIbsgen arithbinaryo..szapco......c...szap.Signed Multiply
6Cw01+f1INSYbDXgen inout string.d......Input from Port to String
INSBYbDX
6DW01+f1INSYwDXgen inout string.d......Input from Port to String
INSWYwDX
6DW03+f1INSYvDXgen inout string.d......Input from Port to String
INSDYdDX
6Ew01+f1OUTSDXXbgen inout string.d......Output String to Port
OUTSBDXXb
6FW01+f1OUTSDXXwgen inout string.d......Output String to Port
OUTSWDXXw
6FW03+f1OUTSDXXvgen inout string.d......Output String to Port
OUTSDDXXd
70tttnJOJbsgen branchcondo.......Jump short if overflow (OF=1)
71tttNJNOJbsgen branchcondo.......Jump short if not overflow (OF=0)
72ttTnJBJbsgen branchcond.......cJump short if below/not above or equal/carry (CF=1)
JNAEJbs
JCJbs
73ttTNJNBJbsgen branchcond.......cJump short if not below/above or equal/not carry (CF=0)
JAEJbs
JNCJbs
74tTtnJZJbsgen branchcond....z...Jump short if zero/equal (ZF=0)
JEJbs
75tTtNJNZJbsgen branchcond....z...Jump short if not zero/not equal (ZF=1)
JNEJbs
76tTTnJBEJbsgen branchcond....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNAJbs
77tTTNJNBEJbsgen branchcond....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JAJbs
78TttnJSJbsgen branchcond...s....Jump short if sign (SF=1)
79TttNJNSJbsgen branchcond...s....Jump short if not sign (SF=0)
7ATtTnJPJbsgen branchcond......p.Jump short if parity/parity even (PF=1)
JPEJbs
7BTtTNJNPJbsgen branchcond......p.Jump short if not parity/parity odd
JPOJbs
7CTTtnJLJbsgen branchcondo..s....Jump short if less/not greater (SF!=OF)
JNGEJbs
7DTTtNJNLJbsgen branchcondo..s....Jump short if not less/greater or equal (SF=OF)
JGEJbs
7ETTTnJLEJbsgen branchcondo..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNGJbs
7FTTTNJNLEJbsgen branchcondo..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JGJbs
80w0LADDEbIbgen arithbinaryo..szapco..szapcAdd
80w1LOREbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
80w2LADCEbIbgen arithbinary.......co..szapco..szapcAdd with Carry
80w3LSBBEbIbgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
80w4LANDEbIbgen logicalo..szapco..sz.pc.....a..o......cLogical AND
80w5LSUBEbIbgen arithbinaryo..szapco..szapcSubtract
80w6LXOREbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
80w7CMPEbIbgen arithbinaryo..szapco..szapcCompare Two Operands
81W0LADDEvqpIvdsgen arithbinaryo..szapco..szapcAdd
81W1LOREvqpIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
81W2LADCEvqpIvdsgen arithbinary.......co..szapco..szapcAdd with Carry
81W3LSBBEvqpIvdsgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
81W4LANDEvqpIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical AND
81W5LSUBEvqpIvdsgen arithbinaryo..szapco..szapcSubtract
81W6LXOREvqpIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
81W7CMPEvqpIvdsgen arithbinaryo..szapco..szapcCompare Two Operands
82w0LADD alias EbIbgen arithbinaryo..szapco..szapcAdd
82w1LOR alias EbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
82w2LADC alias EbIbgen arithbinary.......co..szapco..szapcAdd with Carry
82w3LSBB alias EbIbgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
82w4LAND alias EbIbgen logicalo..szapco..sz.pc.....a..o......cLogical AND
82w5LSUB alias EbIbgen arithbinaryo..szapco..szapcSubtract
82w6LXOR alias EbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
82w7CMP alias EbIbgen arithbinaryo..szapco..szapcCompare Two Operands
82P4+EinvalidInvalid Instruction in 64-Bit Mode
83SW0LADDEvqpIbsgen arithbinaryo..szapco..szapcAdd
83SW103+LOREvqpIbsgen logicalo..szapco..sz.pc.....a..o......cLogical Inclusive OR
83SW2LADCEvqpIbsgen arithbinary.......co..szapco..szapcAdd with Carry
83SW3LSBBEvqpIbsgen arithbinary.......co..szapco..szapcInteger Subtraction with Borrow
83SW403+LANDEvqpIbsgen logicalo..szapco..sz.pc.....a..o......cLogical AND
83SW5LSUBEvqpIbsgen arithbinaryo..szapco..szapcSubtract
83SW603+LXOREvqpIbsgen logicalo..szapco..sz.pc.....a..o......cLogical Exclusive OR
83SW7CMPEvqpIbsgen arithbinaryo..szapco..szapcCompare Two Operands
84dwrTESTEbGbgen arithbinaryo..szapco..sz.pc.....a..o......cLogical Compare
85dWrTESTEvqpGvqpgen arithbinaryo..szapco..sz.pc.....a..o......cLogical Compare
86DwrLXCHGGbEbgen datamovExchange Register/Memory with Register
87DWrLXCHGGvqpEvqpgen datamovExchange Register/Memory with Register
88dwrMOVEbGbgen datamovMove
89dWrMOVEvqpGvqpgen datamovMove
8ADwrMOVGbEbgen datamovMove
8BDwrMOVGvqpEvqpgen datamovMove
8CdrMOVEvqpSwgen datamovMove
8DrLEAGvqpMgen datamovLoad Effective Address
8EDrMOVSwEvqpgen datamovMove
8FW0POPEvgen stackPop a Value from the Stack
8FW0P4+EPOPEvqgen stackPop a Value from the Stack
90+rXCHGZvqprAXgen datamovExchange Register/Memory with Register
90NOPgen controlNo Operation
F390D3no mnemonic nopgen controlNo Operation
F390P4+PAUSEgen controlSpin Loop Hint
98CBWAHALgen converConvert Byte to Word
9803+CWDEEAXAXgen converConvert Word to Doubleword
98P4+ECBWAHALgen converConvert
CWDEEAXAX
CDQERAXEAX
99CWDDXAXgen converConvert Word to Doubleword
9903+CDQEDXEAXgen converConvert Doubleword to Quadword
99P4+ECWDDXAXgen converConvert
CDQEDXEAX
CQORDXRAX
9ACALLFApgen branch stackCall Procedure
9AP4+EinvalidInvalid Instruction in 64-Bit Mode
9BWAITx87fpu control01230123Check pending unmasked floating-point exceptions
FWAIT
9Bno mnemonicprefix x87fpucontrol01230123Wait Prefix
9CPUSHFFwgen stack flgctrlodiszapcPush rFLAGS Register onto the Stack
9C03+PUSHFFwgen stack flgctrlodiszapcPush rFLAGS Register onto the Stack
PUSHFDFd
9CP4+EPUSHFFwgen stack flgctrlodiszapcPush rFLAGS Register onto the Stack
PUSHFQFq
9DPOPFFwgen stack flgctrlodiszapcodiszapcPop Stack into rFLAGS Register
9D03+POPFFwgen stack flgctrlodiszapcodiszapcPop Stack into rFLAGS Register
POPFDFd
9DP4+EPOPFFwgen stack flgctrlodiszapcodiszapcPop Stack into rFLAGS Register
POPFQFq
9ED4SAHFAHgen datamov flgctrl...szapc...szapcStore AH into Flags
9FD4LAHFAHgen datamov flgctrl...szapcLoad Status Flags into AH Register
A0wMOVALObgen datamovMove
A1WMOVrAXOvqpgen datamovMove
A2wMOVObALgen datamovMove
A3WMOVOvqprAXgen datamovMove
A4wMOVSYbXbgen datamov string.d......Move Data from String to String
MOVSBYbXb
A5WMOVSYwXwgen datamov string.d......Move Data from String to String
MOVSWYwXw
A5W03+MOVSYvXvgen datamov string.d......Move Data from String to String
MOVSDYdXd
A5WP4+EMOVSYvqpXvqpgen datamov string.d......Move Data from String to String
MOVSWYwXw
MOVSDYdXd
MOVSQYqpXqp
A6wCMPSYbXbgen arith stringbinary.d......o..szapco..szapcCompare String Operands
CMPSBYbXb
A7WCMPSYwXwgen arith stringbinary.d......o..szapco..szapcCompare String Operands
CMPSWYwXw
A7W03+CMPSYvXvgen arith stringbinary.d......o..szapco..szapcCompare String Operands
CMPSDYdXd
A7WP4+ECMPSYvqpXvqpgen arith stringbinary.d......o..szapco..szapcCompare String Operands
CMPSWYwXw
CMPSDYdXd
CMPSQYqpXqp
A8wTESTALIbgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
A9WTESTrAXIvdsgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
AAwSTOSYbALgen datamov string.d......Store String
STOSBYbAL
ABWSTOSYwAXgen datamov string.d......Store String
STOSWYwAX
ABW03+STOSYveAXgen datamov string.d......Store String
STOSDYdEAX
ABWP4+ESTOSYvqprAXgen datamov string.d......Store String
STOSWYwAX
STOSDYdEAX
STOSQYqpRAX
ACwLODSALXbgen datamov string.d......Load String
LODSBALYb
ADWLODSAXXwgen datamov string.d......Load String
LODSWAXXw
ADW03+LODSeAXXvgen datamov string.d......Load String
LODSDEAXXd
ADWP4+ELODSrAXXvqpgen datamov string.d......Load String
LODSWAXXw
LODSDEAXXd
LODSQRAXXqp
AEwSCASYbALgen arith stringbinary.d......o..szapco..szapcScan String
SCASBYbAL
AFWSCASYwAXgen arith stringbinary.d......o..szapco..szapcScan String
SCASWYwAX
AFW03+SCASYveAXgen arith stringbinary.d......o..szapco..szapcScan String
SCASDYdEAX
AFWP4+ESCASYvqprAXgen arith stringbinary.d......o..szapco..szapcScan String
SCASWYwAX
SCASDYdEAX
SCASQYqpRAX
B0+rMOVZbIbgen datamovMove
B8+rMOVZvqpIvqpgen datamovMove
C0w001+ROLEbIbgen shftroto..szapco..szapco.......Rotate
C0w101+ROREbIbgen shftroto..szapco..szapco.......Rotate
C0w201+RCLEbIbgen shftrot.......co..szapco..szapco.......Rotate
C0w301+RCREbIbgen shftrot.......co..szapco..szapco.......Rotate
C0w401+SHLEbIbgen shftroto..szapco..sz.pco....a.cShift
SALEbIb
C0w501+SHREbIbgen shftroto..szapco..sz.pco....a.cShift
C0w601+U5SAL alias EbIbgen shftroto..szapco..sz.pco....a.cShift
SHL alias EbIb
C0w701+SAREbIbgen shftroto..szapco..sz.pco....a..Shift
C1W001+ROLEvqpIbgen shftroto..szapco..szapco.......Rotate
C1W101+ROREvqpIbgen shftroto..szapco..szapco.......Rotate
C1W201+RCLEvqpIbgen shftrot.......co..szapco..szapco.......Rotate
C1W301+RCREvqpIbgen shftrot.......co..szapco..szapco.......Rotate
C1W401+SHLEvqpIbgen shftroto..szapco..sz.pco....a.cShift
SALEvqpIb
C1W501+SHREvqpIbgen shftroto..szapco..sz.pco....a.cShift
C1w601+U5SAL alias EvqpIbgen shftroto..szapco..sz.pco....a.cShift
SHL alias EvqpIb
C1W701+SAREvqpIbgen shftroto..szapco..sz.pco....a..Shift
C2RETNIwgen branch stackReturn from procedure
C3RETNgen branch stackReturn from procedure
C4rLESESGvMpgen datamov segregLoad Far Pointer
C4P4+EinvalidInvalid Instruction in 64-Bit Mode
C5rLDSDSGvMpgen datamov segregLoad Far Pointer
C5P4+EinvalidInvalid Instruction in 64-Bit Mode
C6w0MOVEbIbgen datamovMove
C7W0MOVEvqpIvdsgen datamovMove
C801+ENTERrBPIwIbgen stackMake Stack Frame for Procedure Parameters
C901+LEAVErBPgen stackHigh Level Procedure Exit
CAfRETFIwgen branch stackReturn from procedure
CBfRETFgen branch stackReturn from procedure
CCfINT3Fvgen break stack..i.......i.......i.....Call to Interrupt Procedure
CDfINTIbFvgen break stack..i.......i.......i.....Call to Interrupt Procedure
CEfINTOFvgen break stacko.........i.......i.......i.....Call to Interrupt Procedure
CFfIRETFwgen break stackodiszapcodiszapcInterrupt Return
CF03+fIRETDFdgen break stackodiszapcodiszapcInterrupt Return
CFEfIRETFwgen break stackodiszapcodiszapcInterrupt Return
IRETDFd
IRETQFqp
D0w0ROLEb1gen shftroto..szapco..szapcRotate
D0w1ROREb1gen shftroto..szapco..szapcRotate
D0w2RCLEb1gen shftrot.......co..szapco..szapcRotate
D0w3RCREb1gen shftrot.......co..szapco..szapcRotate
D0w4SHLEb1gen shftroto..szapco..sz.pc.....a..Shift
SALEb1
D0w5SHREb1gen shftroto..szapco..sz.pc.....a..Shift
D0w6U5SAL alias Eb1gen shftroto..szapco..sz.pc.....a..Shift
SHL alias Eb1
D0w7SAREb1gen shftroto..szapco..sz.pc.....a..Shift
D1W0ROLEvqp1gen shftroto..szapco..szapcRotate
D1W1ROREvqp1gen shftroto..szapco..szapcRotate
D1W2RCLEvqp1gen shftrot.......co..szapco..szapcRotate
D1W3RCREvqp1gen shftrot.......co..szapco..szapcRotate
D1W4SHLEvqp1gen shftroto..szapco..sz.pc.....a..Shift
SALEvqp1
D1W5SHREvqp1gen shftroto..szapco..sz.pc.....a..Shift
D1W6U5SAL alias Evqp1gen shftroto..szapco..sz.pc.....a..Shift
SHL alias Evqp1
D1W7SAREvqp1gen shftroto..szapco..sz.pc.....a..Shift
D2w0ROLEbCLgen shftroto..szapco..szapco.......Rotate
D2w1ROREbCLgen shftroto..szapco..szapco.......Rotate
D2w2RCLEbCLgen shftrot.......co..szapco..szapco.......Rotate
D2w3RCREbCLgen shftrot.......co..szapco..szapco.......Rotate
D2w4SHLEbCLgen shftroto..szapco..sz.pco....a.cShift
SALEbCL
D2w5SHREbCLgen shftroto..szapco..sz.pco....a.cShift
D2w6U5SAL alias EbCLgen shftroto..szapco..sz.pco....a.cShift
SHL alias EbCL
D2w7SAREbCLgen shftroto..szapco..sz.pco....a..Shift
D3W0ROLEvqpCLgen shftroto..szapco..szapco.......Rotate
D3W1ROREvqpCLgen shftroto..szapco..szapco.......Rotate
D3W2RCLEvqpCLgen shftrot.......co..szapco..szapco.......Rotate
D3W3RCREvqpCLgen shftrot.......co..szapco..szapco.......Rotate
D3W4SHLEvqpCLgen shftroto..szapco..sz.pco....a.cShift
SALEvqpCL
D3W5SHREvqpCLgen shftroto..szapco..sz.pco....a.cShift
D3W6U5SAL alias EvqpCLgen shftroto..szapco..sz.pco....a.cShift
SHL alias EvqpCL
D3W7SAREvqpCLgen shftroto..szapco..sz.pc.....a..Shift
D40AAAMALAHgen arithdecimalo..szapc...sz.p.o....a.cASCII Adjust AX After Multiply
D4AMXALAHIbgen arithdecimalo..szapc...sz.p.o....a.cAdjust AX After Multiply
D4P4+EinvalidInvalid Instruction in 64-Bit Mode
D50AAADALAHgen arithdecimalo..szapc...sz.p.o....a.cASCII Adjust AX Before Division
D5ADXALAHIbgen arithdecimalo..szapc...sz.p.o....a.cAdjust AX Before Division
D5P4+EinvalidInvalid Instruction in 64-Bit Mode
D602+D6undefinedUndefined and Reserved; Does not Generate #UD
D602+U7SALCALgen datamov.......cSet AL If Carry
SETALCAL
D6P4+EinvalidInvalid Instruction in 64-Bit Mode
D7XLATALBbgen datamovTable Look-up Translation
XLATBALBb
D8mf0FADDSTMsrx87fpu arith0123.1..0.23Add
FADDSTEST
D8mf1FMULSTMsrx87fpu arith0123.1..0.23Multiply
FMULSTEST
D8mf2FCOMSTESsrx87fpu compar01230123Compare Real
D8D12FCOMSTST1x87fpu compar01230123Compare Real
D8mf3pFCOMPSTESsrx87fpu compar01230123Compare Real and Pop
D8D93pFCOMPSTST1x87fpu compar01230123Compare Real and Pop
D8mf4FSUBSTMsrx87fpu arith0123.1..0.23Subtract
FSUBSTEST
D8mf5FSUBRSTMsrx87fpu arith0123.1..0.23Reverse Subtract
FSUBRSTEST
D8mf6FDIVSTMsrx87fpu arith0123.1..0.23Divide
FDIVSTEST
D8mf7FDIVRSTMsrx87fpu arith0123.1..0.23Reverse Divide
FDIVRSTEST
D9mf0sFLDSTESsrx87fpu datamov0123.1..0.23Load Floating Point Value
D9mf1FXCHSTESTx87fpu datamov0123.1..0.23Exchange Register Contents
D9C91FXCHSTST1x87fpu datamov0123.1..0.23Exchange Register Contents
D9mf2FSTMsrSTx87fpu datamov0123.1..0.23Store Floating Point Value
D9D02FNOPx87fpu control01230123No Operation
D9mf3pFSTPMsrSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
D93D8pFSTP1 part aliasESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
D9303+U16pFSTP1 part alias9ESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
D94FLDENVMex87fpu control01230123Load x87 FPU Environment
D9E04FCHSSTx87fpu arith0123.1..0.23Change Sign
D9E14FABSSTx87fpu arith0123.1..0.23Absolute Value
D9E44FTSTSTx87fpu compar01230123Test
D9E54FXAMSTx87fpu01230123Examine
D95FLDCWMwx87fpu control01230123Load x87 FPU Control Word
D9E85sFLD1STx87fpu ldconst0123.1..0.23Load Constant +1.0
D9E95sFLDL2TSTx87fpu ldconst0123.1..0.23Load Constant logˆ2 10
D9EA5sFLDL2ESTx87fpu ldconst0123.1..0.23Load Constant logˆ2 e
D9EB5sFLDPISTx87fpu ldconst0123.1..0.23Load Constant π
D9EC5sFLDLG2STx87fpu ldconst0123.1..0.23Load Constant logˆ10 2
D9ED5sFLDLN2STx87fpu ldconst0123.1..0.23Load Constant logˆe 2
D9EE5sFLDZSTx87fpu ldconst0123.1..0.23Load Constant +0.0
D96FNSTENVMex87fpu control01230123Store x87 FPU Environment
9BD96FSTENVMex87fpu control01230123Store x87 FPU Environment
D9F06F2XM1STx87fpu trans0123.1..0.23Compute 2ˆx-1
D9F16pFYL2XST1STx87fpu trans0123.1..0.23Compute y × logˆ2 x and Pop
D9F26sFPTANSTx87fpu trans0123.12.0..3Partial Tangent
D9F36pFPATANST1STx87fpu trans0123.1..0.23Partial Arctangent and Pop
D9F46sFXTRACTSTx87fpu arith0123.1..0.23Extract Exponent and Significand
D9F56FPREM1STST1x87fpu arith01230123IEEE Partial Remainder
D9F66FDECSTPx87fpu control0123.1..0.23.0..Decrement Stack-Top Pointer
D9F76FINCSTPx87fpu control0123.1..0.23.0..Increment Stack-Top Pointer
D97FNSTCWMwx87fpu control01230123Store x87 FPU Control Word
9BD97FSTCWMwx87fpu control01230123Store x87 FPU Control Word
D9F87FPREMSTST1x87fpu arith01230123Partial Remainder (for compatibility with i8087 and i287)
D9F97pFYL2XP1ST1STx87fpu trans0123.1..0.23Compute y × logˆ2 (x+1) and Pop
D9FA7FSQRTSTx87fpu arith0123.1..0.23Square Root
D9FB7sFSINCOSSTx87fpu trans0123.12.0..3Sine and Cosine
D9FC7FRNDINTSTx87fpu arith0123.1..0.23Round to Integer
D9FD7FSCALESTST1x87fpu arith0123.1..0.23Scale
D9FE7FSINSTx87fpu trans0123.12.0..3Sine
D9FF7FCOSSTx87fpu trans0123.12.0..3Cosine
DAmF0FIADDSTMdix87fpu arith0123.1..0.23Add
DA0PP+FCMOVBSTESTx87fpu datamov.......c0123.1..0.23Floating-Point Conditional Move - below (CF=1)
DAmF1FIMULSTMdix87fpu arith0123.1..0.23Multiply
DA1PP+FCMOVESTESTx87fpu datamov....z...0123.1..0.23Floating-Point Conditional Move - equal (ZF=1)
DAmF2FICOMSTMdix87fpu compar01230123Compare Integer
DA2PP+FCMOVBESTESTx87fpu datamov....z...0123.1..0.23Floating-Point Conditional Move - below or equal (CF=1 or ZF=1)
DAmF3pFICOMPSTMdix87fpu compar01230123Compare Integer and Pop
DA3PP+FCMOVUSTESTx87fpu datamov......p.0123.1..0.23Floating-Point Conditional Move - unordered (PF=1)
DAmF4FISUBSTMdix87fpu arith0123.1..0.23Subtract
DAmF5FISUBRSTMdix87fpu arith0123.1..0.23Reverse Subtract
DAE9503+PFUCOMPPSTST1x87fpu compar01230123Unordered Compare Floating Point Values and Pop Twice
DAmF6FIDIVSTMdix87fpu arith0123.1..0.23Divide
DAmF7FIDIVRSTMdix87fpu arith0123.1..0.23Reverse Divide
DBmF0sFILDSTMdix87fpu datamov0123.1..0.23Load Integer
DB0PP+FCMOVNBSTESTx87fpu datamov.......c0123.1..0.23Floating-Point Conditional Move - not below (CF=0)
DBmF1P4++pFISTTPMdiSTsse3x87fpu conv0123.1..0.23.0..Store Integer with Truncation
DB1PP+FCMOVNESTESTx87fpu datamov....z...0123.1..0.23Floating-Point Conditional Move - not equal (ZF=0)
DBmF2FISTMdiSTx87fpu datamov0123.1..0.23Store Integer
DB2PP+FCMOVNBESTESTx87fpu datamov....z...0123.1..0.23Floating-Point Conditional Move - below or equal (CF=0 and ZF=0)
DBmF3pFISTPMdiSTx87fpu datamov0123.1..0.23Store Integer and Pop
DB3PP+FCMOVNUSTESTx87fpu datamov......p.0123.1..0.23Floating-Point Conditional Move - not unordered (PF=0)
DBE0400FNENIx87fpu controlEnable NPX Interrupt
9BDBE0400FENIx87fpu controlEnable NPX Interrupt
DBE0401+D10FNENI nopobsol controlTreated as Integer NOP
DBE1400FNDISIx87fpu controlDisable NPX Interrupt
9BDBE1400FDISIx87fpu controlDisable NPX Interrupt
DBE1401+D10FNDISI nopobsol controlTreated as Integer NOP
DBE24FNCLEXx87fpu control01230123Clear Exceptions
9BDBE24FCLEXx87fpu control01230123Clear Exceptions
DBE34FNINITx87fpu control01230000Initialize Floating-Point Unit
9BDBE34FINITx87fpu control01230000Initialize Floating-Point Unit
DBE4402FNSETPMx87fpu controlSet Protected Mode
9BDBE4402FSETPMx87fpu controlSet Protected Mode
DBE4403+D11FNSETPM nopobsol controlTreated as Integer NOP
DB5sFLDSTMerx87fpu datamov0123.1..0.23Load Floating Point Value
DB5PP+FUCOMISTESTx87fpu comparo...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS
DB6PP+FCOMISTESTx87fpu comparo...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS
DB7pFSTPMerSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DCMf0FADDSTMdrx87fpu arith0123.1..0.23Add
DC0FADDESTSTx87fpu arith0123.1..0.23Add
DCMf1FMULSTMdrx87fpu arith0123.1..0.23Multiply
DC1FMULESTSTx87fpu arith0123.1..0.23Multiply
DCMf2FCOMSTMdrx87fpu compar01230123Compare Real
DC2D12FCOM2 alias STESTx87fpu compar01230123Compare Real
DC203+U16FCOM2 alias STESTx87fpu compar01230123Compare Real
DCMf3pFCOMPSTMdrx87fpu compar01230123Compare Real and Pop
DC3D13pFCOMP3 alias STESTx87fpu compar01230123Compare Real and Pop
DC303+U16pFCOMP3 alias STESTx87fpu compar01230123Compare Real and Pop
DCMf4FSUBSTMdrx87fpu arith0123.1..0.23Subtract
DC4FSUBRESTSTx87fpu arith0123.1..0.23Reverse Subtract
DCMf5FSUBRSTMdrx87fpu arith0123.1..0.23Reverse Subtract
DC5FSUBESTSTx87fpu arith0123.1..0.23Subtract
DCMf6FDIVSTMdrx87fpu arith0123.1..0.23Divide
DC6FDIVRESTSTx87fpu arith0123.1..0.23Reverse Divide
DCMf7FDIVRSTMdrx87fpu arith0123.1..0.23Reverse Divide
DC7FDIVESTSTx87fpu arith0123.1..0.23Divide and Pop
DDMf0sFLDSTMdrx87fpu datamov0123.1..0.23Load Floating Point Value
DD0FFREEESTx87fpu control01230123Free Floating-Point Register
DD1P4++pFISTTPMqiSTsse3x87fpu conv0123.1..0.23.0..Store Integer with Truncation
DD1D14FXCH4 alias STESTx87fpu datamov0123.1..0.23Exchange Register Contents
DD103+U16FXCH4 alias STESTx87fpu datamov0123.1..0.23Exchange Register Contents
DDMf2FSTMdrSTx87fpu datamov0123.1..0.23Store Floating Point Value
DD2FSTSTESTx87fpu datamov0123.1..0.23Store Floating Point Value
DDMf3pFSTPMdrSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DD3pFSTPSTESTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DD4FRSTOR ... x87fpu control01230123Restore x87 FPU State
DD403+FUCOMSTESTx87fpu compar01230123Unordered Compare Floating Point Values
DDE1403+FUCOMSTST1x87fpu compar01230123Unordered Compare Floating Point Values
DD503+pFUCOMPSTESTx87fpu compar01230123Unordered Compare Floating Point Values and Pop
DDE9503+pFUCOMPSTST1x87fpu compar01230123Unordered Compare Floating Point Values and Pop
DD6FNSAVE ... x87fpu control012301230000Restore x87 FPU State
9BDD6FSAVE ... x87fpu control012301230000Restore x87 FPU State
DD7FNSTSWMwx87fpu control01230123Store x87 FPU Status Word
9BDD7FSTSWMwx87fpu control01230123Store x87 FPU Status Word
DEMF0FIADDSTMwix87fpu arith0123.1..0.23Add
DE0pFADDPESTSTx87fpu arith0123.1..0.23Add and Pop
DEC10pFADDPST1STx87fpu arith0123.1..0.23Add and Pop
DEMF1FIMULSTMwix87fpu arith0123.1..0.23Multiply
DE1pFMULPESTSTx87fpu arith0123.1..0.23Multiply and Pop
DEC91pFMULPST1STx87fpu arith0123.1..0.23Multiply and Pop
DEMF2FICOMSTMwix87fpu compar01230123Compare Integer
DE2D13pFCOMP5 alias STESTx87fpu compar01230123Compare Real and Pop
DE203+U16pFCOMP5 alias STESTx87fpu compar01230123Compare Real and Pop
DEMF3pFICOMPSTMwix87fpu compar01230123Compare Integer and Pop
DED93PFCOMPPSTST1x87fpu compar01230123Compare Real and Pop Twice
DEMF4FISUBSTMwix87fpu arith0123.1..0.23Subtract
DE4pFSUBRPESTSTx87fpu arith0123.1..0.23Reverse Subtract and Pop
DEE14pFSUBRPST1STx87fpu arith0123.1..0.23Reverse Subtract and Pop
DEMF5FISUBRSTMwix87fpu arith0123.1..0.23Reverse Subtract
DE5pFSUBPESTSTx87fpu arith0123.1..0.23Subtract and Pop
DEE95pFSUBPST1STx87fpu arith0123.1..0.23Subtract and Pop
DEMF6FIDIVSTMwix87fpu arith0123.1..0.23Divide
DE6pFDIVRPESTSTx87fpu arith0123.1..0.23Reverse Divide and Pop
DE6pFDIVRPST1STx87fpu arith0123.1..0.23Reverse Divide and Pop
DEMF7FIDIVRSTMwix87fpu arith0123.1..0.23Reverse Divide
DE7pFDIVPESTSTx87fpu arith0123.1..0.23Divide and Pop
DEF97pFDIVPST1STx87fpu arith0123.1..0.23Divide and Pop
DFMF0sFILDSTMwix87fpu datamov0123.1..0.23Load Integer
DF0D15pFFREEPESTx87fpu control01230123Free Floating-Point Register and Pop
DFMF1P4++pFISTTPMwiSTsse3x87fpu conv0123.1..0.23.0..Store Integer with Truncation
DF1D14FXCH7 alias STESTx87fpu datamov0123.1..0.23Exchange Register Contents
DF103+U16FXCH7 alias STESTx87fpu datamov0123.1..0.23Exchange Register Contents
DFMF2FISTMwiSTx87fpu datamov0123.1..0.23Store Integer
DF2D8pFSTP8 alias ESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DF203+U16pFSTP8 alias ESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DFMF3pFISTPMwiSTx87fpu datamov0123.1..0.23Store Integer and Pop
DF3D8pFSTP9 alias ESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DF303+U16pFSTP9 alias ESTSTx87fpu datamov0123.1..0.23Store Floating Point Value and Pop
DF4sFBLDSTMbcdx87fpu datamov0123.1..0.23Load Binary Coded Decimal
DFE0402+FNSTSWAXx87fpu control01230123Store x87 FPU Status Word
9BDFE0402+FSTSWAXx87fpu control01230123Store x87 FPU Status Word
DF5sFILDSTMqix87fpu datamov0123.1..0.23Load Integer
DF5PP+pFUCOMIPSTESTx87fpu comparo...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF6pFBSTPMbcdSTx87fpu datamov0123.1..0.23Store BCD Integer and Pop
DF6PP+pFCOMIPSTESTx87fpu comparo...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF7pFISTPMqiSTx87fpu datamov0123.1..0.23Store Integer and Pop
E0LOOPNZrCXJbsgen branchcond....z...Decrement count; Jump short if count!=0 and ZF=0
LOOPNErCXJbs
E1LOOPZrCXJbsgen branchcond....z...Decrement count; Jump short if count!=0 and ZF=1
LOOPErCXJbs
E2LOOPrCXJbsgen branchcondDecrement count; Jump short if count!=0
E3JCXZJbsCXgen branchcondJump short if eCX register is 0
JECXZJbsECX
E3P4+EJECXZJbsECXgen branchcondJump short if rCX register is 0
JRCXZJbsRCX
E4wf1INALIbgen inoutInput from Port
E5Wf1INeAXIbgen inoutInput from Port
E6wf1OUTIbALgen inoutOutput to Port
E7Wf1OUTIbeAXgen inoutOutput to Port
E8CALLJvgen branch stackCall Procedure
E8P4+D32ECALLJdsgen branch stackCall Procedure
E9JMPJvgen branchJump
E9P4+D32EJMPJdsgen branchJump
EAJMPFApgen branchJump
EAP4+EinvalidInvalid Instruction in 64-Bit Mode
EBJMPJbsgen branchJump
ECwf1INALDXgen inoutInput from Port
EDWf1INeAXDXgen inoutInput from Port
EEwf1OUTDXALgen inoutOutput to Port
EFWf1OUTDXeAXgen inoutOutput to Port
F0LOCKprefixAssert LOCK# Signal Prefix
F1D6undefinedUndefined and Reserved; Does not Generate #UD
F103+U17INT1 part alias17Fvgen break stack..i.......i.......i.....Call to Interrupt Procedure
ICEBP part alias17Fv
F2REPNZrCXprefix string....z...Repeat String Operation Prefix
REPNErCX
F2UREPrCXprefix stringRepeat String Operation Prefix
F2P4+Mno mnemonicsse2prefixScalar Double-precision Prefix
F3REPZrCXprefix string....z...Repeat String Operation Prefix
REPErCX
F3REPrCXprefix stringRepeat String Operation Prefix
F3P3+Mno mnemonicsseprefixScalar Single-precision Prefix
F40HLTsystemHalt
F5CMCgen flgctrl.......c.......c.......cComplement Carry Flag
F6w0TESTEbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
F6w1U18TEST alias EbIbgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
F6w2NOTEbgen logicalOne's Complement Negation
F6w3NEGEbgen arithbinaryo..szapco..szapcTwo's Complement Negation
F6w4MULAXALEbgen arithbinaryo..szapco......c...szap.Unsigned Multiply
F6w5IMULAXALEbgen arithbinaryo..szapco......c...szap.Signed Multiply
F6w6DIVALAHAXEbgen arithbinaryo..szapco..szapcUnsigned Divide
F6w7IDIVALAHAXEbgen arithbinaryo..szapco..szapcSigned Divide
F7W0TESTEvqpIvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
F7W1U18TEST alias EvqpIvqpgen logicalo..szapco..sz.pc.....a..o......cLogical Compare
F7W2NOTEvqpgen logicalOne's Complement Negation
F7W3NEGEvqpgen arithbinaryo..szapco..szapcTwo's Complement Negation
F7W4MULrDXrAXEvqpgen arithbinaryo..szapco......c...szap.Unsigned Multiply
F7w5IMULrDXrAXEvqpgen arithbinaryo..szapco......c...szap.Signed Multiply
F7w6DIVrDXrAXEvqpgen arithbinaryo..szapco..szapcUnsigned Divide
F7w7IDIVrDXrAXEvqpgen arithbinaryo..szapco..szapcSigned Divide
F8CLCgen flgctrl.......c.......c.......cClear Carry Flag
F9STCgen flgctrl.......c.......c.......CSet Carry Flag
FAf1CLIgen flgctrl..i.......i.......i.....Clear Interrupt Flag
FBf1STIgen flgctrl..i.......i.......I.....Set Interrupt Flag
FCCLDgen flgctrl.d.......d.......d......Clear Direction Flag
FDSTDgen flgctrl.d.......d.......D......Set Direction Flag
FEw0INCEbgen arithbinaryo..szap.o..szap.Increment by 1
FEw1DECEbgen arithbinaryo..szap.o..szap.Decrement by 1
FFW0INCEvqpgen arithbinaryo..szap.o..szap.Increment by 1
FFW1DECEvqpgen arithbinaryo..szap.o..szap.Decrement by 1
FFW2CALLEvgen branch stackCall Procedure
FF2P4+D32ECALLEqgen branch stackCall Procedure
FFW3D19CALLFEptpgen branch stackCall Procedure
FFW4JMPEvgen branchJump
FF4P4+D32EJMPEqgen branchJump
FFW5D19JMPFEptpgen branchJump
FFW6PUSHEvgen stackPop a Value from the Stack
FFW6P4+EPUSHEvqgen stackPop a Value from the Stack
pf0Fposofldsoprocstmrlxmnemonicop1op2op3op4iextgrp1grp2grp3tested fmodif fdef fundef ff valuesdescription, notes                                                  
0F00002+PSLDTMwLDTRsystemStore Local Descriptor Table Register
SLDTRvqpLDTR
0F00102+PSTRMwTRsystemStore Task Register
STRRvqpTR
0F00202+P0LLDTLDTREwsystemLoad Local Descriptor Table Register
0F00302+P0LTRTREwsystemLoad Task Register
0F00402+PVERREwsystem....z.......z...Verify a Segment for Reading
0F00502+PVERWEwsystem....z.......z...Verify a Segment for Writing
0F006IT+JMPEJump to IA-64 Instruction Set
0F01002+SGDTMsGDTRsystemStore Global Descriptor Table Register
0F01102+SIDTMsIDTRsystemStore Interrupt Descriptor Table Register
0F01202+0LGDTGDTRMssystemLoad Global Descriptor Table Register
0F01302+0LIDTIDTRMssystemLoad Interrupt Descriptor Table Register
0F01402+SMSWMwMSWsystemStore Machine Status Word
SMSWRvqpMSW
0F01602+LMSWMSWEwsystemLoad Machine Status Word
0F01704+0INVLPGMsystemInvalidate TLB Entry
0F01F87P4+E0SWAPGSGSI...systemSwap GS Base Register
0F0202+PLARGvqpMwsystem....z.......z...Load Access Rights Byte
LARGvqpRv
0F0302+PLSLGvqpMwsystem....z.......z...Load Segment Limit
LSLGvqpRv
0F0502U20PLOADALL ... system branchodiszapcodiszapcLoad All of the CPU Registers
0F05P4+D21ESYSCALL ... system branchFast System Call
0F0602+0CLTSCR0Clear Task-Switched Flag in CR0
0F0703U20PLOADALL ... system branchodiszapcodiszapcLoad All of the CPU Registers
0F07P4+E0SYSRET ... system branchtransodiszapcodiszapcReturn From Fast System Call
0F0804+0INVDsystemInvalidate Internal Caches
0F0904+0WBINVDsystemWrite Back and Invalidate Cache
0F0B02+UD2gen controlUndefined Instruction
0F0DPP+M22NOPEvgen controlNo Operation
0F1FP4++NOPEvgen controlNo Operation
0F20r03+D230MOVRdCdsystemo..szapco..szapcMove to/from Control Registers
0F20r03+U240MOVHdCdsystemo..szapco..szapcMove to/from Control Registers
0F20rP4+E0MOVRqCqsystemo..szapco..szapcMove to/from Control Registers
0F20rP4+U24E0MOVHqCqsystemo..szapco..szapcMove to/from Control Registers
0F21r03+0MOVRdqpDdqpsystemo..szapco..szapcMove to/from Debug Registers
0F21r03+U240MOVHdqpDdqpsystemo..szapco..szapcMove to/from Debug Registers
0F22r03+D230MOVCdRdsystemo..szapco..szapcMove to/from Control Registers
0F22r03+U240MOVCdHdsystemo..szapco..szapcMove to/from Control Registers
0F22rP4+E0MOVCqRqsystemo..szapco..szapcMove to/from Control Registers
0F22rP4+U24E0MOVCqHqsystemo..szapco..szapcMove to/from Control Registers
0F23r03+0MOVDdqpRdqpsystemo..szapco..szapcMove to/from Debug Registers
0F23r03+U240MOVDdqpRdqpsystemo..szapco..szapcMove to/from Debug Registers
0F24r03-040MOVRdTdsystemo..szapco..szapcMove to/from Test Registers
0F24r03-04U240MOVHdTdsystemo..szapco..szapcMove to/from Test Registers
0F26r03-040MOVTdRdsystemo..szapco..szapcMove to/from Test Registers
0F26r03-04U240MOVTdHdsystemo..szapco..szapcMove to/from Test Registers
0F30P1+0WRMSRMSReCXeAXeDXsystemWrite to Model Specific Register
0F31P1+f2RDTSCEAXEDXI...systemRead Time-Stamp Counter
0F32P1+0RDMSRrAXrDXrCXMSRsystemRead from Model Specific Register
0F33PX+f3RDPMCEAXEDXPMCsystemRead Performance-Monitoring Counters
0F34P2+D25PSYSENTERI...I...I...system branch stack..i.......i.......i.....Fast System Call
0F35P2+D26P0SYSEXITI...rCXrDXsystem branch stacktransFast Return from Fast System Call
0F40tttnrPP+CMOVOGvqpEvqpgen datamovo.......Conditional Move - overflow (OF=1)
0F41tttNrPP+CMOVNOGvqpEvqpgen datamovo.......Conditional Move - not overflow (OF=0)
0F42ttTnrPP+CMOVBGvqpEvqpgen datamov.......cConditional Move - below/not above or equal/carry (CF=1)
CMOVNAEGvqpEvqp
CMOVCGvqpEvqp
0F43ttTNrPP+CMOVNBGvqpEvqpgen datamov.......cConditional Move - not below/above or equal/not carry (CF=0)
CMOVAEGvqpEvqp
CMOVNCGvqpEvqp
0F44tTtnrPP+CMOVZGvqpEvqpgen datamov....z...Conditional Move - zero/equal (ZF=0)
CMOVEGvqpEvqp
0F45tTtNrPP+CMOVNZGvqpEvqpgen datamov....z...Conditional Move - not zero/not equal (ZF=1)
CMOVNEGvqpEvqp
0F46tTTnrPP+CMOVBEGvqpEvqpgen datamov....z..cConditional Move - below or equal/not above (CF=1 AND ZF=1)
CMOVNAGvqpEvqp
0F47tTTNrPP+CMOVNBEGvqpEvqpgen datamov....z..cConditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVAGvqpEvqp
0F48TttnrPP+CMOVSGvqpEvqpgen datamov...s....Conditional Move - sign (SF=1)
0F49TttNrPP+CMOVNSGvqpEvqpgen datamov...s....Conditional Move - not sign (SF=0)
0F4ATtTnrPP+CMOVPGvqpEvqpgen datamov......p.Conditional Move - parity/parity even (PF=1)
CMOVPEGvqpEvqp
0F4BTtTNrPP+CMOVNPGvqpEvqpgen datamov......p.Conditional Move - not parity/parity odd
CMOVPOGvqpEvqp
0F4CTTtnrPP+CMOVLGvqpEvqpgen datamovo..s....Conditional Move - less/not greater (SF!=OF)
CMOVNGEGvqpEvqp
0F4DTTtNrPP+CMOVNLGvqpEvqpgen datamovo..s....Conditional Move - not less/greater or equal (SF=OF)
CMOVGEGvqpEvqp
0F4ETTTnrPP+CMOVLEGvqpEvqpgen datamovo..sz...Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNGGvqpEvqp
0F4FTTTNrPP+CMOVNLEGvqpEvqpgen datamovo..sz...Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVGGvqpEvqp
0F60rPX+PUNPCKLBWPqQdmmxunpackUnpack Low Data
0F61rPX+PUNPCKLWDPqQdmmxunpackUnpack Low Data
0F62rPX+PUNPCKLDQPqQdmmxunpackUnpack Low Data
0F63rPX+PACKSSWBPqQdmmxconverPack with Signed Saturation
0F64rPX+PCMPGTBPqQdmmxcomparCompare Packed Signed Integers for Greater Than
0F65rPX+PCMPGTWPqQdmmxcomparCompare Packed Signed Integers for Greater Than
0F66rPX+PCMPGTDPqQdmmxcomparCompare Packed Signed Integers for Greater Than
0F67rPX+PACKUSWBPqQqmmxconverPack with Unsigned Saturation
0F68rPX+PUNPCKHBWPqQqmmxunpackUnpack High Data
0F69rPX+PUNPCKHWDPqQqmmxunpackUnpack High Data
0F6ArPX+PUNPCKHDQPqQqmmxunpackUnpack High Data
0F6BrPX+PACKSSDWPqQqmmxconverPack with Signed Saturation
0F6ErPX+MOVDPqEdmmxdatamovMove Doubleword
0F6FrPX+MOVQPqQqmmxdatamovMove Quadword
0F712PX+PSRLWPqIbmmxshiftShift Packed Data Right Logical
0F714PX+PSRAWPqIbmmxshiftShift Packed Data Right Arithmetic
0F716PX+PSLLWPqIbmmxshiftShift Packed Data Left Logical
0F722PX+PSRLDQPqIbmmxshiftShift Double Quadword Right Logical
0F724PX+PSRADPqIbmmxshiftShift Packed Data Right Arithmetic
0F726PX+PSLLDPqIbmmxshiftShift Packed Data Left Logical
0F732PX+PSRLQPqIbmmxshiftShift Packed Data Right Logical
0F736PX+PSLLQPqIbmmxshiftShift Packed Data Left Logical
0F74rPX+PCMPEQBPqQqmmxcomparCompare Packed Data for Equal
0F75rPX+PCMPEQWPqQqmmxcomparCompare Packed Data for Equal
0F76rPX+PCMPEQDPqQqmmxcomparCompare Packed Data for Equal
0F77PX+EMMSmmxEmpty MMX Technology State
0F7ErPX+MOVDEdPqmmxdatamovMove Doubleword
0F7FrPX+MOVQQqPqmmxdatamovMove Quadword
0F80tttn03+JOJvgen branchcondo.......Jump short if overflow (OF=1)
0F80tttnP4+D32EJOJdsgen branchcondo.......Jump short if overflow (OF=1)
0F81tttN03+JNOJvgen branchcondo.......Jump short if not overflow (OF=0)
0F81tttNP4+D32EJNOJdsgen branchcondo.......Jump short if not overflow (OF=0)
0F82ttTn03+JBJvgen branchcond.......cJump short if below/not above or equal/carry (CF=1)
JNAEJv
JCJv
0F82ttTnP4+D32EJBJdsgen branchcond.......cJump short if below/not above or equal/carry (CF=1)
JNAEJds
JCJds
0F83ttTN03+JNBJvgen branchcond.......cJump short if not below/above or equal/not carry (CF=0)
JAEJv
JNCJv
0F83ttTNP4+D32EJNBJdsgen branchcond.......cJump short if not below/above or equal/not carry (CF=0)
JAEJds
JNCJds
0F84tTtn03+JZJvgen branchcond....z...Jump short if zero/equal (ZF=0)
JEJv
0F84tTtnP4+D32EJZJdsgen branchcond....z...Jump short if zero/equal (ZF=0)
JEJds
0F85tTtN03+JNZJvgen branchcond....z...Jump short if not zero/not equal (ZF=1)
JNEJv
0F85tTtNP4+D32EJNZJdsgen branchcond....z...Jump short if not zero/not equal (ZF=1)
JNEJds
0F86tTTn03+JBEJvgen branchcond....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNAJv
0F86tTTnP4+D32EJBEJdsgen branchcond....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNAJds
0F87tTTN03+JNBEJvgen branchcond....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JAJv
0F87tTTNP4+D32EJNBEJdsgen branchcond....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JAJds
0F88Tttn03+JSJvgen branchcond...s....Jump short if sign (SF=1)
0F88TttnP4+D32EJSJdsgen branchcond...s....Jump short if sign (SF=1)
0F89TttN03+JNSJvgen branchcond...s....Jump short if not sign (SF=0)
0F89TttNP4+D32EJNSJdsgen branchcond...s....Jump short if not sign (SF=0)
0F8ATtTn03+JPJvgen branchcond......p.Jump short if parity/parity even (PF=1)
JPEJv
0F8ATtTnP4+D32EJPJdsgen branchcond......p.Jump short if parity/parity even (PF=1)
JPEJds
0F8BTtTN03+JNPJvgen branchcond......p.Jump short if not parity/parity odd
JPOJv
0F8BTtTNP4+D32EJNPJdsgen branchcond......p.Jump short if not parity/parity odd
JPOJds
0F8CTTtn03+JLJvgen branchcondo..s....Jump short if less/not greater (SF!=OF)
JNGEJv
0F8CTTtnP4+D32EJLJdsgen branchcondo..s....Jump short if less/not greater (SF!=OF)
JNGEJds
0F8DTTtN03+JNLJvgen branchcondo..s....Jump short if not less/greater or equal (SF=OF)
JGEJv
0F8DTTtNP4+D32EJNLJdsgen branchcondo..s....Jump short if not less/greater or equal (SF=OF)
JGEJds
0F8ETTTn03+JLEJvgen branchcondo..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNGJv
0F8ETTTnP4+D32EJLEJdsgen branchcondo..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNGJds
0F8FTTTN03+JNLEJvgen branchcondo..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JGJv
0F8FTTTNP4+D32EJNLEJdsgen branchcondo..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JGJds
0F90tttn003+D27SETOEbgen datamovo.......Set Byte on Condition - overflow (OF=1)
0F91tttN003+D27SETNOEbgen datamovo.......Set Byte on Condition - not overflow (OF=0)
0F92ttTn003+D27SETBEbgen datamov.......cSet Byte on Condition - below/not above or equal/carry (CF=1)
SETNAEEb
SETCEb
0F93ttTN003+D27SETNBEbgen datamov.......cSet Byte on Condition - not below/above or equal/not carry (CF=0)
SETAEEb
SETNCEb
0F94tTtn003+D27SETZEbgen datamov....z...Set Byte on Condition - zero/equal (ZF=0)
SETEEb
0F95tTtN003+D27SETNZEbgen datamov....z...Set Byte on Condition - not zero/not equal (ZF=1)
SETNEEb
0F96tTTn003+D27SETBEEbgen datamov....z..cSet Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
SETNAEb
0F97tTTN003+D27SETNBEEbgen datamov....z..cSet Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETAEb
0F98Tttn003+D27SETSEbgen datamov...s....Set Byte on Condition - sign (SF=1)
0F99TttN003+D27SETNSEbgen datamov...s....Set Byte on Condition - not sign (SF=0)
0F9ATtTn003+D27SETPEbgen datamov......p.Set Byte on Condition - parity/parity even (PF=1)
SETPEEb
0F9BTtTN003+D27SETNPEbgen datamov......p.Set Byte on Condition - not parity/parity odd
SETPOEb
0F9CTTtn003+D27SETLEbgen datamovo..s....Set Byte on Condition - less/not greater (SF!=OF)
SETNGEEb
0F9DTTtN003+D27SETNLEbgen datamovo..s....Set Byte on Condition - not less/greater or equal (SF=OF)
SETGEEb
0F9ETTTn003+D27SETLEEbgen datamovo..sz...Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNGEb
0F9FTTTN003+D27SETNLEEbgen datamovo..sz...Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETGEb
0FA0Sre03+PUSHFSgen stack segregPush Word, Doubleword or Quadword Onto the Stack
0FA1Sre03+POPFSgen stack segregPop a Value from the Stack
0FA204++CPUID ... gen controlCPU Identification
0FA303+BTEvqpGvqpgen bito..szapc.......co..szap.Bit Test
0FA4d03+SHLDEvqpGvqpIbgen shftroto..szapco..sz.pco....a.cDouble Precision Shift Left
0FA5d03+SHLDEvqpGvqpCLgen shftroto..szapco..sz.pco....a.cDouble Precision Shift Left
0FA8SrE03+PUSHGSgen stack segregPush Word, Doubleword or Quadword Onto the Stack
0FA9SrE03+POPGSgen stack segregPop a Value from the Stack
0FAA03++SRSMFodiszapcodiszapcResume from System Management Mode
0FAB03+LBTSEvqpGvqpgen bito..szapc.......co..szap.Bit Test and Set
0FACd03+SHRDEvqpGvqpIbgen shftroto..szapco..sz.pco....a.cDouble Precision Shift Right
0FADd03+SHRDEvqpGvqpCLgen shftroto..szapco..sz.pco....a.cDouble Precision Shift Right
0FAE0P2++FXSAVE ... smSave x87 FPU, MMX, XMM, and MXCSR State
0FAE0P4+EFXSAVE ... smSave x87 FPU, MMX, XMM, and MXCSR State
0FAE1P2++FXRSTOR ... smRestore x87 FPU, MMX, XMM, and MXCSR State
0FAE1P4+EFXRSTOR ... smRestore x87 FPU, MMX, XMM, and MXCSR State
0FAFDWr03+IMULGvqpEvqpgen arithbinaryo..szapco......c...szap.Signed Multiply
0FB0dwr04+LCMPXCHGEbALGbgen datamov arithbinaryo..szapco..szapcCompare and Exchange
0FB1dWr04+LCMPXCHGEvqprAXGvqpgen datamov arithbinaryo..szapco..szapcCompare and Exchange
0FB2sRer03+D28LSSSSGvqpMptpgen datamov segregLoad Far Pointer
0FB303+LBTREvqpGvqpgen bito..szapc.......co..szap.Bit Test and Reset
0FB4Srer03+D28LFSFSGvqpMptpgen datamov segregLoad Far Pointer
0FB5SrEr03+D28LGSGSGvqpMptpgen datamov segregLoad Far Pointer
0FB6Dwr03+MOVZXGvqpEbgen converMove with Zero-Extend
0FB7DWr03+MOVZXGvqpEwgen converMove with Zero-Extend
0FB8IT+JMPEJump to IA-64 Instruction Set
0FB902+M29UDGEgen controlUndefined Instruction
0FBA403+BTEvqpIbgen bito..szapc.......co..szap.Bit Test
0FBA503+LBTSEvqpIbgen bito..szapc.......co..szap.Bit Test and Set
0FBA603+LBTREvqpIbgen bito..szapc.......co..szap.Bit Test and Reset
0FBA703+LBTCEvqpIbgen bito..szapc.......co..szap.Bit Test and Complement
0FBB03+LBTCEvqpGvqpgen bito..szapc.......co..szap.Bit Test and Complement
0FBC03+D30BSFGvqpEvqpgen bito..szapc....z...o..s.apcBit Scan Forward
0FBD03+D30BSRGvqpEvqpgen bito..szapc....z...o..s.apcBit Scan Reverse
0FBEDwr03+MOVSXGvqpEbgen converMove with Sign-Extension
0FBFDWr03+MOVSXGvqpEwgen converMove with Sign-Extension
0FC0dwr04+LXADDEbGbgen datamov arithbinaryo..szapco..szapcExchange and Add
0FC1dWr04+LXADDEvqpGvqpgen datamov arithbinaryo..szapco..szapcExchange and Add
0FC71P1+LCMPXCHG8B ... gen datamov arithbinary....z.......z...Compare and Exchange Bytes
0FC71P4+D31ELCMPXCHG8B ... gen datamov arithbinary....z.......z...Compare and Exchange Bytes
0FC71P4+D31ELCMPXCHG16B ... gen datamov arithbinary....z.......z...Compare and Exchange Bytes
0FC8+r04+BSWAPZvqpgen datamovByte Swap
0FD1rPX+PSRLWPqQqmmxshiftShift Packed Data Right Logical
0FD2rPX+PSRLDPqQqmmxshiftShift Packed Data Right Logical
0FD3rPX+PSRLQPqQqmmxshiftShift Packed Data Right Logical
0FD5rPX+PMULLWPqQqmmxarithMultiply Packed Signed Integers and Store Low Result
0FD8rPX+PSUBUSBPqQqmmxarithSubtract Packed Unsigned Integers with Unsigned Saturation
0FD9rPX+PSUBUSWPqQqmmxarithSubtract Packed Unsigned Integers with Unsigned Saturation
0FDBrPX+PANDPqQdmmxlogicalLogical AND
0FDCrPX+PADDUSBPqQqmmxarithAdd Packed Unsigned Integers with Unsigned Saturation
0FDDrPX+PADDUSWPqQqmmxarithAdd Packed Unsigned Integers with Unsigned Saturation
0FDFrPX+PANDNPqQqmmxlogicalLogical AND NOT
0FE1rPX+PSRAWPqQqmmxshiftShift Packed Data Right Arithmetic
0FE2rPX+PSRADPqQqmmxshiftShift Packed Data Right Arithmetic
0FE5rPX+PMULHWPqQqmmxarithMultiply Packed Signed Integers and Store High Result
0FE8rPX+PSUBSBPqQqmmxarithSubtract Packed Signed Integers with Signed Saturation
0FE9rPX+PSUBSWPqQqmmxarithSubtract Packed Signed Integers with Signed Saturation
0FEBrPX+PORPqQqmmxlogicalBitwise Logical OR
0FECrPX+PADDSBPqQqmmxarithAdd Packed Signed Integers with Signed Saturation
0FEDrPX+PADDSWPqQqmmxarithAdd Packed Signed Integers with Signed Saturation
0FEFrPX+PXORPqQqmmxlogicalLogical Exclusive OR
0FF1rPX+PSLLWPqQqmmxshiftShift Packed Data Left Logical
0FF2rPX+PSLLDPqQqmmxshiftShift Packed Data Left Logical
0FF3rPX+PSLLQPqQqmmxshiftShift Packed Data Left Logical
0FF5rPX+PMADDWDPqQdmmxarithMultiply and Add Packed Integers
0FF8rPX+PSUBBPqQqmmxarithSubtract Packed Integers
0FF9rPX+PSUBWPqQqmmxarithSubtract Packed Integers
0FFArPX+PSUBDPqQqmmxarithSubtract Packed Integers
0FFCrPX+PADDBPqQqmmxarithAdd Packed Integers
0FFDrPX+PADDWPqQqmmxarithAdd Packed Integers
0FFErPX+PADDDPqQqmmxarithAdd Packed Integers

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General notes:

    1. OPCODE.LST, Revision 4.51, 15 Oct 1999 © Potemkin's Hackers Group 1994...1999
    1. The microarchitecture of Intel and AMD CPU's, By Agner Fog, Copyright © 1996 - 2006.
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, PAUSE instruction
    1. LAHF nad SAHF are invalid on early steppings of EM64T architecture; that's why they need CPUID.80000001H:ECX.LAHF-SAHF[bit 0]
    1. sandpile.org -- IA-32 architecture -- opcode groups
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 3: System Programming Guide, Interrupt and Exception Handling
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (D9 /3, mod = 11b, DF /2, mod = 11b, DF /3, mod = 11b) in the instruction stream, it will execute it as follows: FSTP ST(i)
    1. Christian Ludloff wrote: While FSTP (D9 /3, mod < 11b), FSTP8 (DF /2, mod = 11b), and FSTP9 (DF /3, mod = 11b) do signal stack underflow, FSTP1 (D9 /3, mod = 11b) does not.
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOM ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /3, mod = 11b, DE /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOMP ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DD /1, mod = 11b, DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FXCH ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel® Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
    1. AMD64 architecture does not enable 64-bit offset: AMD64 Architecture Programmer's Manual Volume 3: If the operand-size is 32 or 64 bits, the operand is a 16-bit selector followed by a 32-bit offset.
    1. sandpile.org -- IA-32 architecture -- two byte opcodes
    2. www.x86.org - The LOADALL Instruction
    1. On AMD64 architecture, SYSCALL is valid also in legacy mode
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
    1. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: If CPUID.80000001H:ECX.4, CR8 can be read and written in legacy mode using a LOCK prefix instead of a REX prefix to specify the additional opcode bit.
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
    1. On AMD64 architecture, SYSENTER is valid only in legacy mode.
    1. On AMD64 architecture, SYSEXIT is not valid in long mode.
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
    1. AMD64 architecture does not enable 64-bit operands: AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: Executing LFS, LGS, or LSS with a 64-bit operand size only loads a 32-bit general purpose register and the specified segment register
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes
    1. On AMD64 architecture, BSF and BSR instructions act differently if the content of the source operand is 0
    1. CMPXCHG16B is invalid on early steppings of AMD64 architecture
    1. Use of operand-size prefix in 64-bit mode may result in implementation-dependent behaviour; on AMD64 architecture, this prefix acts as expected

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

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