one-byte quick reference

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

two-byte (0F..) quick reference

00 01 02 03 05 06 07 08 09 0B 0D 1F 20 21 22 23 30 31 32 33 34 35 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 60 61 62 63 64 65 66 67 68 69 6A 6B 6E 6F 71 72 73 74 75 76 77 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B9 BA BB BC BD BE BF C0 C1 C7 C8 C9 CA CB CC CD CE CF D1 D2 D3 D5 D8 D9 DB DC DD DF E1 E2 E5 E8 E9 EB EC ED EF F1 F2 F3 F5 F8 F9 FA FC FD FE
pf0Fposooprocstmrlxmnemonicop1op2op3op4iexttested fmodif fdef fundef ff valuesdescription, notes                                                  
00rLADD r/m8 r8o..szapco..szapcAdd
01rLADD r/m16/32/64 r16/32/64o..szapco..szapcAdd
02rADD r8 r/m8o..szapco..szapcAdd
03rADD r16/32/64 r/m16/32/64o..szapco..szapcAdd
04ADDAL imm8o..szapco..szapcAdd
05ADDrAX imm16/32o..szapco..szapcAdd
06EinvalidInvalid Instruction in 64-Bit Mode
07EinvalidInvalid Instruction in 64-Bit Mode
08rLOR r/m8 r8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
09rLOR r/m16/32/64 r16/32/64o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0ArOR r8 r/m8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0BrOR r16/32/64 r/m16/32/64o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0CORAL imm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0DORrAX imm16/32o..szapco..sz.pc.....a..o......cLogical Inclusive OR
0EEinvalidInvalid Instruction in 64-Bit Mode
0Ftwo-byte
10rLADC r/m8 r8.......co..szapco..szapcAdd with Carry
11rLADC r/m16/32/64 r16/32/64.......co..szapco..szapcAdd with Carry
12rADC r8 r/m8.......co..szapco..szapcAdd with Carry
13rADC r16/32/64 r/m16/32/64.......co..szapco..szapcAdd with Carry
14ADCAL imm8.......co..szapco..szapcAdd with Carry
15ADCrAX imm16/32.......co..szapco..szapcAdd with Carry
16EinvalidInvalid Instruction in 64-Bit Mode
17EinvalidInvalid Instruction in 64-Bit Mode
18rLSBB r/m8 r8.......co..szapco..szapcInteger Subtraction with Borrow
19rLSBB r/m16/32/64 r16/32/64.......co..szapco..szapcInteger Subtraction with Borrow
1ArSBB r8 r/m8.......co..szapco..szapcInteger Subtraction with Borrow
1BrSBB r16/32/64 r/m16/32/64.......co..szapco..szapcInteger Subtraction with Borrow
1CSBBAL imm8.......co..szapco..szapcInteger Subtraction with Borrow
1DSBBrAX imm16/32.......co..szapco..szapcInteger Subtraction with Borrow
1EEinvalidInvalid Instruction in 64-Bit Mode
1FEinvalidInvalid Instruction in 64-Bit Mode
20rLAND r/m8 r8o..szapco..sz.pc.....a..o......cLogical AND
21rLAND r/m16/32/64 r16/32/64o..szapco..sz.pc.....a..o......cLogical AND
22rAND r8 r/m8o..szapco..sz.pc.....a..o......cLogical AND
23rAND r16/32/64 r/m16/32/64o..szapco..sz.pc.....a..o......cLogical AND
24ANDAL imm8o..szapco..sz.pc.....a..o......cLogical AND
25ANDrAX imm16/32o..szapco..sz.pc.....a..o......cLogical AND
26EnullNull Prefix in 64-bit Mode
27EinvalidInvalid Instruction in 64-Bit Mode
28rLSUB r/m8 r8o..szapco..szapcSubtract
29rLSUB r/m16/32/64 r16/32/64o..szapco..szapcSubtract
2ArSUB r8 r/m8o..szapco..szapcSubtract
2BrSUB r16/32/64 r/m16/32/64o..szapco..szapcSubtract
2CSUBAL imm8o..szapco..szapcSubtract
2DSUBrAX imm16/32o..szapco..szapcSubtract
2EEundefined(branch hint prefixes have no effect in 64-bit mode)
2EEnullNull Prefix in 64-bit Mode
2FEinvalidInvalid Instruction in 64-Bit Mode
30rLXOR r/m8 r8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
31rLXOR r/m16/32/64 r16/32/64o..szapco..sz.pc.....a..o......cLogical Exclusive OR
32rXOR r8 r/m8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
33rXOR r16/32/64 r/m16/32/64o..szapco..sz.pc.....a..o......cLogical Exclusive OR
34XORAL imm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
35XORrAX imm16/32o..szapco..sz.pc.....a..o......cLogical Exclusive OR
36EnullNull Prefix in 64-bit Mode
37EinvalidInvalid Instruction in 64-Bit Mode
38rCMP r/m8 r8o..szapco..szapcCompare Two Operands
39rCMP r/m16/32/64 r16/32/64o..szapco..szapcCompare Two Operands
3ArCMP r8 r/m8o..szapco..szapcCompare Two Operands
3BrCMP r16/32/64 r/m16/32/64o..szapco..szapcCompare Two Operands
3CCMPAL imm8o..szapco..szapcCompare Two Operands
3DCMPrAX imm16/32o..szapco..szapcCompare Two Operands
3EEundefined(branch hint prefixes have no effect in 64-bit mode)
3EEnullNull Prefix in 64-bit Mode
3FEinvalidInvalid Instruction in 64-Bit Mode
40EREX
41EREX.BExtension of the r/m field, base field, or opcode reg field
42EREX.XExtension of the SIB index field
43EREX.XB
44EREX.RExtension of the ModR/M reg field
45EREX.RB
46EREX.RX
47EREX.RXB
48EREX.W64 Bit Operand Size
49EREX.WB
4AEREX.WX
4BEREX.WXB
4CEREX.WR
4DEREX.WRB
4EEREX.WRX
4FEREX.WRXB
50+rEPUSH r64/16Push Word, Doubleword or Quadword Onto the Stack
58+rEPOP r64/16Pop a Value from the Stack
60EinvalidInvalid Instruction in 64-Bit Mode
61EinvalidInvalid Instruction in 64-Bit Mode
62EinvalidInvalid Instruction in 64-Bit Mode
63rEMOVSXD r32/64 r/m32Move with Sign-Extension
64Eundefined(branch hint prefixes have no effect in 64-bit mode)
65GSGSGS segment override prefix
65undefined(used only with Jcc instructions)
66no mnemonicOperand-size override prefix
66Mno mnemonicsse2Precision-size override prefix
67no mnemonicAddress-size override prefix
68PUSH imm16/32Push Word, Doubleword or Quadword Onto the Stack
69IMUL r16/32/64 r/m16/32/64 imm16/32o..szapco......c...szap.Signed Multiply
6APUSH imm8Push Word, Doubleword or Quadword Onto the Stack
6BIMUL r16/32/64 r/m16/32/64 imm8o..szapco......c...szap.Signed Multiply
6Cf1INS m8DX.d......Input from Port to String
INSB m8DX
6Df1INS m16DX.d......Input from Port to String
INSW m16DX
6Df1INS m16/32DX.d......Input from Port to String
INSD m32DX
6Ef1OUTSDX m8.d......Output String to Port
OUTSBDX m8
6Ff1OUTSDX m16.d......Output String to Port
OUTSWDX m16
6Ff1OUTSDX m16/32.d......Output String to Port
OUTSDDX m32
70JO rel8o.......Jump short if overflow (OF=1)
71JNO rel8o.......Jump short if not overflow (OF=0)
72JB rel8.......cJump short if below/not above or equal/carry (CF=1)
JNAE rel8
JC rel8
73JNB rel8.......cJump short if not below/above or equal/not carry (CF=0)
JAE rel8
JNC rel8
74JZ rel8....z...Jump short if zero/equal (ZF=0)
JE rel8
75JNZ rel8....z...Jump short if not zero/not equal (ZF=1)
JNE rel8
76JBE rel8....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNA rel8
77JNBE rel8....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JA rel8
78JS rel8...s....Jump short if sign (SF=1)
79JNS rel8...s....Jump short if not sign (SF=0)
7AJP rel8......p.Jump short if parity/parity even (PF=1)
JPE rel8
7BJNP rel8......p.Jump short if not parity/parity odd
JPO rel8
7CJL rel8o..s....Jump short if less/not greater (SF!=OF)
JNGE rel8
7DJNL rel8o..s....Jump short if not less/greater or equal (SF=OF)
JGE rel8
7EJLE rel8o..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel8
7FJNLE rel8o..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel8
800LADD r/m8 imm8o..szapco..szapcAdd
801LOR r/m8 imm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
802LADC r/m8 imm8.......co..szapco..szapcAdd with Carry
803LSBB r/m8 imm8.......co..szapco..szapcInteger Subtraction with Borrow
804LAND r/m8 imm8o..szapco..sz.pc.....a..o......cLogical AND
805LSUB r/m8 imm8o..szapco..szapcSubtract
806LXOR r/m8 imm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
807CMP r/m8 imm8o..szapco..szapcCompare Two Operands
810LADD r/m16/32/64 imm16/32o..szapco..szapcAdd
811LOR r/m16/32/64 imm16/32o..szapco..sz.pc.....a..o......cLogical Inclusive OR
812LADC r/m16/32/64 imm16/32.......co..szapco..szapcAdd with Carry
813LSBB r/m16/32/64 imm16/32.......co..szapco..szapcInteger Subtraction with Borrow
814LAND r/m16/32/64 imm16/32o..szapco..sz.pc.....a..o......cLogical AND
815LSUB r/m16/32/64 imm16/32o..szapco..szapcSubtract
816LXOR r/m16/32/64 imm16/32o..szapco..sz.pc.....a..o......cLogical Exclusive OR
817CMP r/m16/32/64 imm16/32o..szapco..szapcCompare Two Operands
82EinvalidInvalid Instruction in 64-Bit Mode
830LADD r/m16/32/64 imm8o..szapco..szapcAdd
831LOR r/m16/32/64 imm8o..szapco..sz.pc.....a..o......cLogical Inclusive OR
832LADC r/m16/32/64 imm8.......co..szapco..szapcAdd with Carry
833LSBB r/m16/32/64 imm8.......co..szapco..szapcInteger Subtraction with Borrow
834LAND r/m16/32/64 imm8o..szapco..sz.pc.....a..o......cLogical AND
835LSUB r/m16/32/64 imm8o..szapco..szapcSubtract
836LXOR r/m16/32/64 imm8o..szapco..sz.pc.....a..o......cLogical Exclusive OR
837CMP r/m16/32/64 imm8o..szapco..szapcCompare Two Operands
84rTEST r/m8 r8o..szapco..sz.pc.....a..o......cLogical Compare
85rTEST r/m16/32/64 r16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
86rLXCHG r8 r/m8Exchange Register/Memory with Register
87rLXCHG r16/32/64 r/m16/32/64Exchange Register/Memory with Register
88rMOV r/m8 r8Move
89rMOV r/m16/32/64 r16/32/64Move
8ArMOV r8 r/m8Move
8BrMOV r16/32/64 r/m16/32/64Move
8CrMOV r/m16/32/64 Sreg Move
8DrLEA r16/32/64 mLoad Effective Address
8ErMOV Sreg r/m16/32/64Move
8F0EPOP r/m64/16Pop a Value from the Stack
90+rXCHG r16/32/64rAXExchange Register/Memory with Register
90NOPNo Operation
F390D3no mnemonic nopNo Operation
F390PAUSESpin Loop Hint
98ECBWAHALConvert
CWDEEAXAX
CDQERAXEAX
99ECWDDXAXConvert
CDQEDXEAX
CQORDXRAX
9AEinvalidInvalid Instruction in 64-Bit Mode
9BWAIT01230123Check pending unmasked floating-point exceptions
FWAIT
9Bno mnemonic01230123Wait Prefix
9CEPUSHFodiszapcPush rFLAGS Register onto the Stack
PUSHFQ
9DEPOPFodiszapcodiszapcPop Stack into rFLAGS Register
POPFQ
9ED4SAHFAH...szapc...szapcStore AH into Flags
9FD4LAHFAH...szapcLoad Status Flags into AH Register
A0MOVAL moffs8Move
A1MOVrAX moffs16/32/64Move
A2MOV moffs8ALMove
A3MOV moffs16/32/64rAXMove
A4MOVS m8 m8.d......Move Data from String to String
MOVSB m8 m8
A5EMOVS m16/32/64 m16/32/64.d......Move Data from String to String
MOVSW m16 m16
MOVSD m32 m32
MOVSQ m64 m64
A6CMPS m8 m8.d......o..szapco..szapcCompare String Operands
CMPSB m8 m8
A7ECMPS m16/32/64 m16/32/64.d......o..szapco..szapcCompare String Operands
CMPSW m16 m16
CMPSD m32 m32
CMPSQ m64 m64
A8TESTAL imm8o..szapco..sz.pc.....a..o......cLogical Compare
A9TESTrAX imm16/32o..szapco..sz.pc.....a..o......cLogical Compare
AASTOS m8AL.d......Store String
STOSB m8AL
ABESTOS m16/32/64rAX.d......Store String
STOSW m16AX
STOSD m32EAX
STOSQ m64RAX
ACLODSAL m8.d......Load String
LODSBAL m8
ADELODSrAX m16/32/64.d......Load String
LODSWAX m16
LODSDEAX m32
LODSQRAX m64
AESCAS m8AL.d......o..szapco..szapcScan String
SCASB m8AL
AFESCAS m16/32/64rAX.d......o..szapco..szapcScan String
SCASW m16AX
SCASD m32EAX
SCASQ m64RAX
B0+rMOV r8 imm8Move
B8+rMOV r16/32/64 imm16/32/64Move
C00ROL r/m8 imm8o..szapco..szapco.......Rotate
C01ROR r/m8 imm8o..szapco..szapco.......Rotate
C02RCL r/m8 imm8.......co..szapco..szapco.......Rotate
C03RCR r/m8 imm8.......co..szapco..szapco.......Rotate
C04SHL r/m8 imm8o..szapco..sz.pco....a.cShift
SAL r/m8 imm8
C05SHR r/m8 imm8o..szapco..sz.pco....a.cShift
C06U5SAL r/m8 imm8o..szapco..sz.pco....a.cShift
SHL r/m8 imm8
C07SAR r/m8 imm8o..szapco..sz.pco....a..Shift
C10ROL r/m16/32/64 imm8o..szapco..szapco.......Rotate
C11ROR r/m16/32/64 imm8o..szapco..szapco.......Rotate
C12RCL r/m16/32/64 imm8.......co..szapco..szapco.......Rotate
C13RCR r/m16/32/64 imm8.......co..szapco..szapco.......Rotate
C14SHL r/m16/32/64 imm8o..szapco..sz.pco....a.cShift
SAL r/m16/32/64 imm8
C15SHR r/m16/32/64 imm8o..szapco..sz.pco....a.cShift
C16U5SAL r/m16/32/64 imm8o..szapco..sz.pco....a.cShift
SHL r/m16/32/64 imm8
C17SAR r/m16/32/64 imm8o..szapco..sz.pco....a..Shift
C2RETN imm16Return from procedure
C3RETNReturn from procedure
C4EinvalidInvalid Instruction in 64-Bit Mode
C5EinvalidInvalid Instruction in 64-Bit Mode
C60MOV r/m8 imm8Move
C70MOV r/m16/32/64 imm16/32Move
C8ENTERrBP imm16 imm8Make Stack Frame for Procedure Parameters
C9LEAVErBPHigh Level Procedure Exit
CAfRETF imm16Return from procedure
CBfRETFReturn from procedure
CCfINT3..i.......i.......i.....Call to Interrupt Procedure
CDfINT imm8..i.......i.......i.....Call to Interrupt Procedure
CEfINTOo.........i.......i.......i.....Call to Interrupt Procedure
CFEfIRETodiszapcodiszapcInterrupt Return
IRETD
IRETQ
D00ROL r/m81o..szapco..szapcRotate
D01ROR r/m81o..szapco..szapcRotate
D02RCL r/m81.......co..szapco..szapcRotate
D03RCR r/m81.......co..szapco..szapcRotate
D04SHL r/m81o..szapco..sz.pc.....a..Shift
SAL r/m81
D05SHR r/m81o..szapco..sz.pc.....a..Shift
D06U5SAL r/m81o..szapco..sz.pc.....a..Shift
SHL r/m81
D07SAR r/m81o..szapco..sz.pc.....a..Shift
D10ROL r/m16/32/641o..szapco..szapcRotate
D11ROR r/m16/32/641o..szapco..szapcRotate
D12RCL r/m16/32/641.......co..szapco..szapcRotate
D13RCR r/m16/32/641.......co..szapco..szapcRotate
D14SHL r/m16/32/641o..szapco..sz.pc.....a..Shift
SAL r/m16/32/641
D15SHR r/m16/32/641o..szapco..sz.pc.....a..Shift
D16U5SAL r/m16/32/641o..szapco..sz.pc.....a..Shift
SHL r/m16/32/641
D17SAR r/m16/32/641o..szapco..sz.pc.....a..Shift
D20ROL r/m8CLo..szapco..szapco.......Rotate
D21ROR r/m8CLo..szapco..szapco.......Rotate
D22RCL r/m8CL.......co..szapco..szapco.......Rotate
D23RCR r/m8CL.......co..szapco..szapco.......Rotate
D24SHL r/m8CLo..szapco..sz.pco....a.cShift
SAL r/m8CL
D25SHR r/m8CLo..szapco..sz.pco....a.cShift
D26U5SAL r/m8CLo..szapco..sz.pco....a.cShift
SHL r/m8CL
D27SAR r/m8CLo..szapco..sz.pco....a..Shift
D30ROL r/m16/32/64CLo..szapco..szapco.......Rotate
D31ROR r/m16/32/64CLo..szapco..szapco.......Rotate
D32RCL r/m16/32/64CL.......co..szapco..szapco.......Rotate
D33RCR r/m16/32/64CL.......co..szapco..szapco.......Rotate
D34SHL r/m16/32/64CLo..szapco..sz.pco....a.cShift
SAL r/m16/32/64CL
D35SHR r/m16/32/64CLo..szapco..sz.pco....a.cShift
D36U5SAL r/m16/32/64CLo..szapco..sz.pco....a.cShift
SHL r/m16/32/64CL
D37SAR r/m16/32/64CLo..szapco..sz.pc.....a..Shift
D4EinvalidInvalid Instruction in 64-Bit Mode
D5EinvalidInvalid Instruction in 64-Bit Mode
D6EinvalidInvalid Instruction in 64-Bit Mode
D7XLATAL m8Table Look-up Translation
XLATBAL m8
D80FADDST m32real0123.1..0.23Add
FADDST STi
D81FMULST m32real0123.1..0.23Multiply
FMULST STi
D82FCOMST STi/m32real01230123Compare Real
D8D12FCOMSTST101230123Compare Real
D83pFCOMPST STi/m32real01230123Compare Real and Pop
D8D93pFCOMPSTST101230123Compare Real and Pop
D84FSUBST m32real0123.1..0.23Subtract
FSUBST STi
D85FSUBRST m32real0123.1..0.23Reverse Subtract
FSUBRST STi
D86FDIVST m32real0123.1..0.23Divide
FDIVST STi
D87FDIVRST m32real0123.1..0.23Reverse Divide
FDIVRST STi
D90sFLDST STi/m32real0123.1..0.23Load Floating Point Value
D91FXCHST STi 0123.1..0.23Exchange Register Contents
D9C91FXCHSTST10123.1..0.23Exchange Register Contents
D92FST m32realST0123.1..0.23Store Floating Point Value
D9D02FNOP01230123No Operation
D93pFSTP m32realST0123.1..0.23Store Floating Point Value and Pop
D93D8pFSTP1 STi ST0123.1..0.23Store Floating Point Value and Pop
D93U16pFSTP1 STi ST0123.1..0.23Store Floating Point Value and Pop
D94FLDENV m14/2801230123Load x87 FPU Environment
D9E04FCHSST0123.1..0.23Change Sign
D9E14FABSST0123.1..0.23Absolute Value
D9E44FTSTST01230123Test
D9E54FXAMST01230123Examine
D95FLDCW m1601230123Load x87 FPU Control Word
D9E85sFLD1ST0123.1..0.23Load Constant +1.0
D9E95sFLDL2TST0123.1..0.23Load Constant logˆ2 10
D9EA5sFLDL2EST0123.1..0.23Load Constant logˆ2 e
D9EB5sFLDPIST0123.1..0.23Load Constant π
D9EC5sFLDLG2ST0123.1..0.23Load Constant logˆ10 2
D9ED5sFLDLN2ST0123.1..0.23Load Constant logˆe 2
D9EE5sFLDZST0123.1..0.23Load Constant +0.0
D96FNSTENV m14/2801230123Store x87 FPU Environment
9BD96FSTENV m14/2801230123Store x87 FPU Environment
D9F06F2XM1ST0123.1..0.23Compute 2ˆx-1
D9F16pFYL2XST1ST0123.1..0.23Compute y × logˆ2 x and Pop
D9F26sFPTANST0123.12.0..3Partial Tangent
D9F36pFPATANST1ST0123.1..0.23Partial Arctangent and Pop
D9F46sFXTRACTST0123.1..0.23Extract Exponent and Significand
D9F56FPREM1STST101230123IEEE Partial Remainder
D9F66FDECSTP0123.1..0.23.0..Decrement Stack-Top Pointer
D9F76FINCSTP0123.1..0.23.0..Increment Stack-Top Pointer
D97FNSTCW m1601230123Store x87 FPU Control Word
9BD97FSTCW m1601230123Store x87 FPU Control Word
D9F87FPREMSTST101230123Partial Remainder (for compatibility with i8087 and i287)
D9F97pFYL2XP1ST1ST0123.1..0.23Compute y × logˆ2 (x+1) and Pop
D9FA7FSQRTST0123.1..0.23Square Root
D9FB7sFSINCOSST0123.12.0..3Sine and Cosine
D9FC7FRNDINTST0123.1..0.23Round to Integer
D9FD7FSCALESTST10123.1..0.23Scale
D9FE7FSINST0123.12.0..3Sine
D9FF7FCOSST0123.12.0..3Cosine
DA0FIADDST m32int0123.1..0.23Add
DA0FCMOVBST STi .......c0123.1..0.23Floating-Point Conditional Move - below (CF=1)
DA1FIMULST m32int0123.1..0.23Multiply
DA1FCMOVEST STi ....z...0123.1..0.23Floating-Point Conditional Move - equal (ZF=1)
DA2FICOMST m32int01230123Compare Integer
DA2FCMOVBEST STi ....z...0123.1..0.23Floating-Point Conditional Move - below or equal (CF=1 or ZF=1)
DA3pFICOMPST m32int01230123Compare Integer and Pop
DA3FCMOVUST STi ......p.0123.1..0.23Floating-Point Conditional Move - unordered (PF=1)
DA4FISUBST m32int0123.1..0.23Subtract
DA5FISUBRST m32int0123.1..0.23Reverse Subtract
DAE95PFUCOMPPSTST101230123Unordered Compare Floating Point Values and Pop Twice
DA6FIDIVST m32int0123.1..0.23Divide
DA7FIDIVRST m32int0123.1..0.23Reverse Divide
DB0sFILDST m32int0123.1..0.23Load Integer
DB0FCMOVNBST STi .......c0123.1..0.23Floating-Point Conditional Move - not below (CF=0)
DB1pFISTTP m32intSTsse30123.1..0.23.0..Store Integer with Truncation
DB1FCMOVNEST STi ....z...0123.1..0.23Floating-Point Conditional Move - not equal (ZF=0)
DB2FIST m32intST0123.1..0.23Store Integer
DB2FCMOVNBEST STi ....z...0123.1..0.23Floating-Point Conditional Move - below or equal (CF=0 and ZF=0)
DB3pFISTP m32intST0123.1..0.23Store Integer and Pop
DB3FCMOVNUST STi ......p.0123.1..0.23Floating-Point Conditional Move - not unordered (PF=0)
DBE04D10FNENI nopTreated as Integer NOP
DBE14D10FNDISI nopTreated as Integer NOP
DBE24FNCLEX01230123Clear Exceptions
9BDBE24FCLEX01230123Clear Exceptions
DBE34FNINIT01230000Initialize Floating-Point Unit
9BDBE34FINIT01230000Initialize Floating-Point Unit
DBE44D11FNSETPM nopTreated as Integer NOP
DB5sFLDST m80real0123.1..0.23Load Floating Point Value
DB5FUCOMIST STi o...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS
DB6FCOMIST STi o...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS
DB7pFSTP m80realST0123.1..0.23Store Floating Point Value and Pop
DC0FADDST m64real0123.1..0.23Add
DC0FADD STi ST0123.1..0.23Add
DC1FMULST m64real0123.1..0.23Multiply
DC1FMUL STi ST0123.1..0.23Multiply
DC2FCOMST m64real01230123Compare Real
DC2D12FCOM2ST STi 01230123Compare Real
DC2U16FCOM2ST STi 01230123Compare Real
DC3pFCOMPST m64real01230123Compare Real and Pop
DC3D13pFCOMP3ST STi 01230123Compare Real and Pop
DC3U16pFCOMP3ST STi 01230123Compare Real and Pop
DC4FSUBST m64real0123.1..0.23Subtract
DC4FSUBR STi ST0123.1..0.23Reverse Subtract
DC5FSUBRST m64real0123.1..0.23Reverse Subtract
DC5FSUB STi ST0123.1..0.23Subtract
DC6FDIVST m64real0123.1..0.23Divide
DC6FDIVR STi ST0123.1..0.23Reverse Divide
DC7FDIVRST m64real0123.1..0.23Reverse Divide
DC7FDIV STi ST0123.1..0.23Divide and Pop
DD0sFLDST m64real0123.1..0.23Load Floating Point Value
DD0FFREE STi 01230123Free Floating-Point Register
DD1pFISTTP m64intSTsse30123.1..0.23.0..Store Integer with Truncation
DD1D14FXCH4ST STi 0123.1..0.23Exchange Register Contents
DD1U16FXCH4ST STi 0123.1..0.23Exchange Register Contents
DD2FST m64realST0123.1..0.23Store Floating Point Value
DD2FSTST STi 0123.1..0.23Store Floating Point Value
DD3pFSTP m64realST0123.1..0.23Store Floating Point Value and Pop
DD3pFSTPST STi 0123.1..0.23Store Floating Point Value and Pop
DD4FRSTOR ... 01230123Restore x87 FPU State
DD4FUCOMST STi 01230123Unordered Compare Floating Point Values
DDE14FUCOMSTST101230123Unordered Compare Floating Point Values
DD5pFUCOMPST STi 01230123Unordered Compare Floating Point Values and Pop
DDE95pFUCOMPSTST101230123Unordered Compare Floating Point Values and Pop
DD6FNSAVE ... 012301230000Restore x87 FPU State
9BDD6FSAVE ... 012301230000Restore x87 FPU State
DD7FNSTSW m1601230123Store x87 FPU Status Word
9BDD7FSTSW m1601230123Store x87 FPU Status Word
DE0FIADDST m16int0123.1..0.23Add
DE0pFADDP STi ST0123.1..0.23Add and Pop
DEC10pFADDPST1ST0123.1..0.23Add and Pop
DE1FIMULST m16int0123.1..0.23Multiply
DE1pFMULP STi ST0123.1..0.23Multiply and Pop
DEC91pFMULPST1ST0123.1..0.23Multiply and Pop
DE2FICOMST m16int01230123Compare Integer
DE2D13pFCOMP5ST STi 01230123Compare Real and Pop
DE2U16pFCOMP5ST STi 01230123Compare Real and Pop
DE3pFICOMPST m16int01230123Compare Integer and Pop
DED93PFCOMPPSTST101230123Compare Real and Pop Twice
DE4FISUBST m16int0123.1..0.23Subtract
DE4pFSUBRP STi ST0123.1..0.23Reverse Subtract and Pop
DEE14pFSUBRPST1ST0123.1..0.23Reverse Subtract and Pop
DE5FISUBRST m16int0123.1..0.23Reverse Subtract
DE5pFSUBP STi ST0123.1..0.23Subtract and Pop
DEE95pFSUBPST1ST0123.1..0.23Subtract and Pop
DE6FIDIVST m16int0123.1..0.23Divide
DE6pFDIVRP STi ST0123.1..0.23Reverse Divide and Pop
DE6pFDIVRPST1ST0123.1..0.23Reverse Divide and Pop
DE7FIDIVRST m16int0123.1..0.23Reverse Divide
DE7pFDIVP STi ST0123.1..0.23Divide and Pop
DEF97pFDIVPST1ST0123.1..0.23Divide and Pop
DF0sFILDST m16int0123.1..0.23Load Integer
DF0D15pFFREEP STi 01230123Free Floating-Point Register and Pop
DF1pFISTTP m16intSTsse30123.1..0.23.0..Store Integer with Truncation
DF1D14FXCH7ST STi 0123.1..0.23Exchange Register Contents
DF1U16FXCH7ST STi 0123.1..0.23Exchange Register Contents
DF2FIST m16intST0123.1..0.23Store Integer
DF2D8pFSTP8 STi ST0123.1..0.23Store Floating Point Value and Pop
DF2U16pFSTP8 STi ST0123.1..0.23Store Floating Point Value and Pop
DF3pFISTP m16intST0123.1..0.23Store Integer and Pop
DF3D8pFSTP9 STi ST0123.1..0.23Store Floating Point Value and Pop
DF3U16pFSTP9 STi ST0123.1..0.23Store Floating Point Value and Pop
DF4sFBLDST m80dec0123.1..0.23Load Binary Coded Decimal
DFE04FNSTSWAX01230123Store x87 FPU Status Word
9BDFE04FSTSWAX01230123Store x87 FPU Status Word
DF5sFILDST m64int0123.1..0.23Load Integer
DF5pFUCOMIPST STi o...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF6pFBSTP m80decST0123.1..0.23Store BCD Integer and Pop
DF6pFCOMIPST STi o...z.pc .1..o...z.pc .1..o.......Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF7pFISTP m64intST0123.1..0.23Store Integer and Pop
E0LOOPNZrCX rel8....z...Decrement count; Jump short if count!=0 and ZF=0
LOOPNErCX rel8
E1LOOPZrCX rel8....z...Decrement count; Jump short if count!=0 and ZF=1
LOOPErCX rel8
E2LOOPrCX rel8Decrement count; Jump short if count!=0
E3EJECXZ rel8ECXJump short if rCX register is 0
JRCXZ rel8RCX
E4f1INAL imm8Input from Port
E5f1INeAX imm8Input from Port
E6f1OUT imm8ALOutput to Port
E7f1OUT imm8eAXOutput to Port
E8D32ECALL rel32Call Procedure
E9D32EJMP rel32Jump
EAEinvalidInvalid Instruction in 64-Bit Mode
EBJMP rel8Jump
ECf1INALDXInput from Port
EDf1INeAXDXInput from Port
EEf1OUTDXALOutput to Port
EFf1OUTDXeAXOutput to Port
F0LOCKAssert LOCK# Signal Prefix
F1D6undefinedUndefined and Reserved; Does not Generate #UD
F1U17INT1..i.......i.......i.....Call to Interrupt Procedure
ICEBP
F2REPNZrCX....z...Repeat String Operation Prefix
REPNErCX
F2UREPrCXRepeat String Operation Prefix
F2Mno mnemonicsse2Scalar Double-precision Prefix
F3REPZrCX....z...Repeat String Operation Prefix
REPErCX
F3REPrCXRepeat String Operation Prefix
F3Mno mnemonicsseScalar Single-precision Prefix
F40HLTHalt
F5CMC.......c.......c.......cComplement Carry Flag
F60TEST r/m8 imm8o..szapco..sz.pc.....a..o......cLogical Compare
F61U18TEST r/m8 imm8o..szapco..sz.pc.....a..o......cLogical Compare
F62NOT r/m8One's Complement Negation
F63NEG r/m8o..szapco..szapcTwo's Complement Negation
F64MULAXAL r/m8o..szapco......c...szap.Unsigned Multiply
F65IMULAXAL r/m8o..szapco......c...szap.Signed Multiply
F66DIVALAHAX r/m8o..szapco..szapcUnsigned Divide
F67IDIVALAHAX r/m8o..szapco..szapcSigned Divide
F70TEST r/m16/32/64 imm16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
F71U18TEST r/m16/32/64 imm16/32/64o..szapco..sz.pc.....a..o......cLogical Compare
F72NOT r/m16/32/64One's Complement Negation
F73NEG r/m16/32/64o..szapco..szapcTwo's Complement Negation
F74MULrDXrAX r/m16/32/64o..szapco......c...szap.Unsigned Multiply
F75IMULrDXrAX r/m16/32/64o..szapco......c...szap.Signed Multiply
F76DIVrDXrAX r/m16/32/64o..szapco..szapcUnsigned Divide
F77IDIVrDXrAX r/m16/32/64o..szapco..szapcSigned Divide
F8CLC.......c.......c.......cClear Carry Flag
F9STC.......c.......c.......CSet Carry Flag
FAf1CLI..i.......i.......i.....Clear Interrupt Flag
FBf1STI..i.......i.......I.....Set Interrupt Flag
FCCLD.d.......d.......d......Clear Direction Flag
FDSTD.d.......d.......D......Set Direction Flag
FE0INC r/m8o..szap.o..szap.Increment by 1
FE1DEC r/m8o..szap.o..szap.Decrement by 1
FF0INC r/m16/32/64o..szap.o..szap.Increment by 1
FF1DEC r/m16/32/64o..szap.o..szap.Decrement by 1
FF2D32ECALL r/m64Call Procedure
FF3D19CALLF r/m16:16/32/64Call Procedure
FF4D32EJMP r/m64Jump
FF5D19JMPF r/m16:16/32/64Jump
FF6EPUSH r/m64/16Pop a Value from the Stack
pf0Fposooprocstmrlxmnemonicop1op2op3op4iexttested fmodif fdef fundef ff valuesdescription, notes                                                  
0F000PSLDT m16LDTRStore Local Descriptor Table Register
SLDT r16/32/64LDTR
0F001PSTR m16TRStore Task Register
STR r16/32/64TR
0F002P0LLDTLDTR r/m16Load Local Descriptor Table Register
0F003P0LTRTR r/m16Load Task Register
0F004PVERR r/m16....z.......z...Verify a Segment for Reading
0F005PVERW r/m16....z.......z...Verify a Segment for Writing
0F010SGDT mGDTRStore Global Descriptor Table Register
0F011SIDT mIDTRStore Interrupt Descriptor Table Register
0F0120LGDTGDTR mLoad Global Descriptor Table Register
0F0130LIDTIDTR mLoad Interrupt Descriptor Table Register
0F014SMSW m16MSWStore Machine Status Word
SMSW r16/32/64MSW
0F016LMSWMSW r/m16Load Machine Status Word
0F0170INVLPG mInvalidate TLB Entry
0F01F87E0SWAPGSGSI...Swap GS Base Register
0F02PLAR r16/32/64 m16....z.......z...Load Access Rights Byte
LAR r16/32/64 r16/32
0F03PLSL r16/32/64 m16....z.......z...Load Segment Limit
LSL r16/32/64 r16/32
0F05D21ESYSCALL ... Fast System Call
0F060CLTSCR0Clear Task-Switched Flag in CR0
0F07E0SYSRET ... odiszapcodiszapcReturn From Fast System Call
0F080INVDInvalidate Internal Caches
0F090WBINVDWrite Back and Invalidate Cache
0F0BUD2Undefined Instruction
0F0DM22NOP r/m16/32No Operation
0F1FNOP r/m16/32No Operation
0F20rE0MOV r64 CRn o..szapco..szapcMove to/from Control Registers
0F20rU24E0MOV r64 CRn o..szapco..szapcMove to/from Control Registers
0F21r0MOV r32/64 DRn o..szapco..szapcMove to/from Debug Registers
0F21rU240MOV r32/64 DRn o..szapco..szapcMove to/from Debug Registers
0F22rE0MOV CRn r64o..szapco..szapcMove to/from Control Registers
0F22rU24E0MOV CRn r64o..szapco..szapcMove to/from Control Registers
0F23r0MOV DRn r32/64o..szapco..szapcMove to/from Debug Registers
0F23rU240MOV DRn r32/64o..szapco..szapcMove to/from Debug Registers
0F300WRMSRMSReCXeAXeDXWrite to Model Specific Register
0F31f2RDTSCEAXEDXI...Read Time-Stamp Counter
0F320RDMSRrAXrDXrCXMSRRead from Model Specific Register
0F33f3RDPMCEAXEDXPMCRead Performance-Monitoring Counters
0F34D25PSYSENTERI...I...I.....i.......i.......i.....Fast System Call
0F35D26P0SYSEXITI...rCXrDXFast Return from Fast System Call
0F40rCMOVO r16/32/64 r/m16/32/64o.......Conditional Move - overflow (OF=1)
0F41rCMOVNO r16/32/64 r/m16/32/64o.......Conditional Move - not overflow (OF=0)
0F42rCMOVB r16/32/64 r/m16/32/64.......cConditional Move - below/not above or equal/carry (CF=1)
CMOVNAE r16/32/64 r/m16/32/64
CMOVC r16/32/64 r/m16/32/64
0F43rCMOVNB r16/32/64 r/m16/32/64.......cConditional Move - not below/above or equal/not carry (CF=0)
CMOVAE r16/32/64 r/m16/32/64
CMOVNC r16/32/64 r/m16/32/64
0F44rCMOVZ r16/32/64 r/m16/32/64....z...Conditional Move - zero/equal (ZF=0)
CMOVE r16/32/64 r/m16/32/64
0F45rCMOVNZ r16/32/64 r/m16/32/64....z...Conditional Move - not zero/not equal (ZF=1)
CMOVNE r16/32/64 r/m16/32/64
0F46rCMOVBE r16/32/64 r/m16/32/64....z..cConditional Move - below or equal/not above (CF=1 AND ZF=1)
CMOVNA r16/32/64 r/m16/32/64
0F47rCMOVNBE r16/32/64 r/m16/32/64....z..cConditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVA r16/32/64 r/m16/32/64
0F48rCMOVS r16/32/64 r/m16/32/64...s....Conditional Move - sign (SF=1)
0F49rCMOVNS r16/32/64 r/m16/32/64...s....Conditional Move - not sign (SF=0)
0F4ArCMOVP r16/32/64 r/m16/32/64......p.Conditional Move - parity/parity even (PF=1)
CMOVPE r16/32/64 r/m16/32/64
0F4BrCMOVNP r16/32/64 r/m16/32/64......p.Conditional Move - not parity/parity odd
CMOVPO r16/32/64 r/m16/32/64
0F4CrCMOVL r16/32/64 r/m16/32/64o..s....Conditional Move - less/not greater (SF!=OF)
CMOVNGE r16/32/64 r/m16/32/64
0F4DrCMOVNL r16/32/64 r/m16/32/64o..s....Conditional Move - not less/greater or equal (SF=OF)
CMOVGE r16/32/64 r/m16/32/64
0F4ErCMOVLE r16/32/64 r/m16/32/64o..sz...Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNG r16/32/64 r/m16/32/64
0F4FrCMOVNLE r16/32/64 r/m16/32/64o..sz...Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVG r16/32/64 r/m16/32/64
0F60rPUNPCKLBW mm mm/m64 mmxUnpack Low Data
0F61rPUNPCKLWD mm mm/m64 mmxUnpack Low Data
0F62rPUNPCKLDQ mm mm/m64 mmxUnpack Low Data
0F63rPACKSSWB mm mm/m64 mmxPack with Signed Saturation
0F64rPCMPGTB mm mm/m64 mmxCompare Packed Signed Integers for Greater Than
0F65rPCMPGTW mm mm/m64 mmxCompare Packed Signed Integers for Greater Than
0F66rPCMPGTD mm mm/m64 mmxCompare Packed Signed Integers for Greater Than
0F67rPACKUSWB mm mm/m64 mmxPack with Unsigned Saturation
0F68rPUNPCKHBW mm mm/m64 mmxUnpack High Data
0F69rPUNPCKHWD mm mm/m64 mmxUnpack High Data
0F6ArPUNPCKHDQ mm mm/m64 mmxUnpack High Data
0F6BrPACKSSDW mm mm/m64 mmxPack with Signed Saturation
0F6ErMOVD mm r/m32mmxMove Doubleword
0F6FrMOVQ mm mm/m64 mmxMove Quadword
0F712PSRLW mm imm8mmxShift Packed Data Right Logical
0F714PSRAW mm imm8mmxShift Packed Data Right Arithmetic
0F716PSLLW mm imm8mmxShift Packed Data Left Logical
0F722PSRLDQ mm imm8mmxShift Double Quadword Right Logical
0F724PSRAD mm imm8mmxShift Packed Data Right Arithmetic
0F726PSLLD mm imm8mmxShift Packed Data Left Logical
0F732PSRLQ mm imm8mmxShift Packed Data Right Logical
0F736PSLLQ mm imm8mmxShift Packed Data Left Logical
0F74rPCMPEQB mm mm/m64 mmxCompare Packed Data for Equal
0F75rPCMPEQW mm mm/m64 mmxCompare Packed Data for Equal
0F76rPCMPEQD mm mm/m64 mmxCompare Packed Data for Equal
0F77EMMSmmxEmpty MMX Technology State
0F7ErMOVD r/m32 mm mmxMove Doubleword
0F7FrMOVQ mm/m64 mm mmxMove Quadword
0F80D32EJO rel32o.......Jump short if overflow (OF=1)
0F81D32EJNO rel32o.......Jump short if not overflow (OF=0)
0F82D32EJB rel32.......cJump short if below/not above or equal/carry (CF=1)
JNAE rel32
JC rel32
0F83D32EJNB rel32.......cJump short if not below/above or equal/not carry (CF=0)
JAE rel32
JNC rel32
0F84D32EJZ rel32....z...Jump short if zero/equal (ZF=0)
JE rel32
0F85D32EJNZ rel32....z...Jump short if not zero/not equal (ZF=1)
JNE rel32
0F86D32EJBE rel32....z..cJump short if below or equal/not above (CF=1 AND ZF=1)
JNA rel32
0F87D32EJNBE rel32....z..cJump short if not below or equal/above (CF=0 AND ZF=0)
JA rel32
0F88D32EJS rel32...s....Jump short if sign (SF=1)
0F89D32EJNS rel32...s....Jump short if not sign (SF=0)
0F8AD32EJP rel32......p.Jump short if parity/parity even (PF=1)
JPE rel32
0F8BD32EJNP rel32......p.Jump short if not parity/parity odd
JPO rel32
0F8CD32EJL rel32o..s....Jump short if less/not greater (SF!=OF)
JNGE rel32
0F8DD32EJNL rel32o..s....Jump short if not less/greater or equal (SF=OF)
JGE rel32
0F8ED32EJLE rel32o..sz...Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel32
0F8FD32EJNLE rel32o..sz...Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel32
0F900D27SETO r/m8o.......Set Byte on Condition - overflow (OF=1)
0F910D27SETNO r/m8o.......Set Byte on Condition - not overflow (OF=0)
0F920D27SETB r/m8.......cSet Byte on Condition - below/not above or equal/carry (CF=1)
SETNAE r/m8
SETC r/m8
0F930D27SETNB r/m8.......cSet Byte on Condition - not below/above or equal/not carry (CF=0)
SETAE r/m8
SETNC r/m8
0F940D27SETZ r/m8....z...Set Byte on Condition - zero/equal (ZF=0)
SETE r/m8
0F950D27SETNZ r/m8....z...Set Byte on Condition - not zero/not equal (ZF=1)
SETNE r/m8
0F960D27SETBE r/m8....z..cSet Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
SETNA r/m8
0F970D27SETNBE r/m8....z..cSet Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETA r/m8
0F980D27SETS r/m8...s....Set Byte on Condition - sign (SF=1)
0F990D27SETNS r/m8...s....Set Byte on Condition - not sign (SF=0)
0F9A0D27SETP r/m8......p.Set Byte on Condition - parity/parity even (PF=1)
SETPE r/m8
0F9B0D27SETNP r/m8......p.Set Byte on Condition - not parity/parity odd
SETPO r/m8
0F9C0D27SETL r/m8o..s....Set Byte on Condition - less/not greater (SF!=OF)
SETNGE r/m8
0F9D0D27SETNL r/m8o..s....Set Byte on Condition - not less/greater or equal (SF=OF)
SETGE r/m8
0F9E0D27SETLE r/m8o..sz...Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNG r/m8
0F9F0D27SETNLE r/m8o..sz...Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETG r/m8
0FA0PUSHFSPush Word, Doubleword or Quadword Onto the Stack
0FA1POPFSPop a Value from the Stack
0FA2CPUID ... CPU Identification
0FA3BT r/m16/32/64 r16/32/64o..szapc.......co..szap.Bit Test
0FA4SHLD r/m16/32/64 r16/32/64 imm8o..szapco..sz.pco....a.cDouble Precision Shift Left
0FA5SHLD r/m16/32/64 r16/32/64CLo..szapco..sz.pco....a.cDouble Precision Shift Left
0FA8PUSHGSPush Word, Doubleword or Quadword Onto the Stack
0FA9POPGSPop a Value from the Stack
0FAASRSModiszapcodiszapcResume from System Management Mode
0FABLBTS r/m16/32/64 r16/32/64o..szapc.......co..szap.Bit Test and Set
0FACSHRD r/m16/32/64 r16/32/64 imm8o..szapco..sz.pco....a.cDouble Precision Shift Right
0FADSHRD r/m16/32/64 r16/32/64CLo..szapco..sz.pco....a.cDouble Precision Shift Right
0FAE0EFXSAVE ... Save x87 FPU, MMX, XMM, and MXCSR State
0FAE1EFXRSTOR ... Restore x87 FPU, MMX, XMM, and MXCSR State
0FAFrIMUL r16/32/64 r/m16/32/64o..szapco......c...szap.Signed Multiply
0FB0rLCMPXCHG r/m8AL r8o..szapco..szapcCompare and Exchange
0FB1rLCMPXCHG r/m16/32/64rAX r16/32/64o..szapco..szapcCompare and Exchange
0FB2rD28LSSSS r16/32/64 m16:16/32/64Load Far Pointer
0FB3LBTR r/m16/32/64 r16/32/64o..szapc.......co..szap.Bit Test and Reset
0FB4rD28LFSFS r16/32/64 m16:16/32/64Load Far Pointer
0FB5rD28LGSGS r16/32/64 m16:16/32/64Load Far Pointer
0FB6rMOVZX r16/32/64 r/m8Move with Zero-Extend
0FB7rMOVZX r16/32/64 r/m16Move with Zero-Extend
0FB9M29UD r r/mUndefined Instruction
0FBA4BT r/m16/32/64 imm8o..szapc.......co..szap.Bit Test
0FBA5LBTS r/m16/32/64 imm8o..szapc.......co..szap.Bit Test and Set
0FBA6LBTR r/m16/32/64 imm8o..szapc.......co..szap.Bit Test and Reset
0FBA7LBTC r/m16/32/64 imm8o..szapc.......co..szap.Bit Test and Complement
0FBBLBTC r/m16/32/64 r16/32/64o..szapc.......co..szap.Bit Test and Complement
0FBCD30BSF r16/32/64 r/m16/32/64o..szapc....z...o..s.apcBit Scan Forward
0FBDD30BSR r16/32/64 r/m16/32/64o..szapc....z...o..s.apcBit Scan Reverse
0FBErMOVSX r16/32/64 r/m8Move with Sign-Extension
0FBFrMOVSX r16/32/64 r/m16Move with Sign-Extension
0FC0rLXADD r/m8 r8o..szapco..szapcExchange and Add
0FC1rLXADD r/m16/32/64 r16/32/64o..szapco..szapcExchange and Add
0FC71D31ELCMPXCHG8B ... ....z.......z...Compare and Exchange Bytes
0FC71D31ELCMPXCHG16B ... ....z.......z...Compare and Exchange Bytes
0FC8+rBSWAP r16/32/64Byte Swap
0FD1rPSRLW mm mm/m64 mmxShift Packed Data Right Logical
0FD2rPSRLD mm mm/m64 mmxShift Packed Data Right Logical
0FD3rPSRLQ mm mm/m64 mmxShift Packed Data Right Logical
0FD5rPMULLW mm mm/m64 mmxMultiply Packed Signed Integers and Store Low Result
0FD8rPSUBUSB mm mm/m64 mmxSubtract Packed Unsigned Integers with Unsigned Saturation
0FD9rPSUBUSW mm mm/m64 mmxSubtract Packed Unsigned Integers with Unsigned Saturation
0FDBrPAND mm mm/m64 mmxLogical AND
0FDCrPADDUSB mm mm/m64 mmxAdd Packed Unsigned Integers with Unsigned Saturation
0FDDrPADDUSW mm mm/m64 mmxAdd Packed Unsigned Integers with Unsigned Saturation
0FDFrPANDN mm mm/m64 mmxLogical AND NOT
0FE1rPSRAW mm mm/m64 mmxShift Packed Data Right Arithmetic
0FE2rPSRAD mm mm/m64 mmxShift Packed Data Right Arithmetic
0FE5rPMULHW mm mm/m64 mmxMultiply Packed Signed Integers and Store High Result
0FE8rPSUBSB mm mm/m64 mmxSubtract Packed Signed Integers with Signed Saturation
0FE9rPSUBSW mm mm/m64 mmxSubtract Packed Signed Integers with Signed Saturation
0FEBrPOR mm mm/m64 mmxBitwise Logical OR
0FECrPADDSB mm mm/m64 mmxAdd Packed Signed Integers with Signed Saturation
0FEDrPADDSW mm mm/m64 mmxAdd Packed Signed Integers with Signed Saturation
0FEFrPXOR mm mm/m64 mmxLogical Exclusive OR
0FF1rPSLLW mm mm/m64 mmxShift Packed Data Left Logical
0FF2rPSLLD mm mm/m64 mmxShift Packed Data Left Logical
0FF3rPSLLQ mm mm/m64 mmxShift Packed Data Left Logical
0FF5rPMADDWD mm mm/m64 mmxMultiply and Add Packed Integers
0FF8rPSUBB mm mm/m64 mmxSubtract Packed Integers
0FF9rPSUBW mm mm/m64 mmxSubtract Packed Integers
0FFArPSUBD mm mm/m64 mmxSubtract Packed Integers
0FFCrPADDB mm mm/m64 mmxAdd Packed Integers
0FFDrPADDW mm mm/m64 mmxAdd Packed Integers
0FFErPADDD mm mm/m64 mmxAdd Packed Integers

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General notes:

    1. OPCODE.LST, Revision 4.51, 15 Oct 1999 © Potemkin's Hackers Group 1994...1999
    1. The microarchitecture of Intel and AMD CPU's, By Agner Fog, Copyright © 1996 - 2006.
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, PAUSE instruction
    1. LAHF nad SAHF are invalid on early steppings of EM64T architecture; that's why they need CPUID.80000001H:ECX.LAHF-SAHF[bit 0]
    1. sandpile.org -- IA-32 architecture -- opcode groups
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 3: System Programming Guide, Interrupt and Exception Handling
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (D9 /3, mod = 11b, DF /2, mod = 11b, DF /3, mod = 11b) in the instruction stream, it will execute it as follows: FSTP ST(i)
    1. Christian Ludloff wrote: While FSTP (D9 /3, mod < 11b), FSTP8 (DF /2, mod = 11b), and FSTP9 (DF /3, mod = 11b) do signal stack underflow, FSTP1 (D9 /3, mod = 11b) does not.
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOM ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /3, mod = 11b, DE /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOMP ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DD /1, mod = 11b, DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FXCH ST(i)
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel® Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
    1. AMD64 architecture does not enable 64-bit offset: AMD64 Architecture Programmer's Manual Volume 3: If the operand-size is 32 or 64 bits, the operand is a 16-bit selector followed by a 32-bit offset.
    1. sandpile.org -- IA-32 architecture -- two byte opcodes
    2. www.x86.org - The LOADALL Instruction
    1. On AMD64 architecture, SYSCALL is valid also in legacy mode
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
    1. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: If CPUID.80000001H:ECX.4, CR8 can be read and written in legacy mode using a LOCK prefix instead of a REX prefix to specify the additional opcode bit.
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
    1. On AMD64 architecture, SYSENTER is valid only in legacy mode.
    1. On AMD64 architecture, SYSEXIT is not valid in long mode.
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
    1. AMD64 architecture does not enable 64-bit operands: AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: Executing LFS, LGS, or LSS with a 64-bit operand size only loads a 32-bit general purpose register and the specified segment register
    1. Intel® 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes
    1. On AMD64 architecture, BSF and BSR instructions act differently if the content of the source operand is 0
    1. CMPXCHG16B is invalid on early steppings of AMD64 architecture
    1. Use of operand-size prefix in 64-bit mode may result in implementation-dependent behaviour; on AMD64 architecture, this prefix acts as expected

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

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